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The following comes from Patterson & Hennessy Computer Org. and Design (5th ed., p. 390):

How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, assuming a 32-bit address?

My question is, how can we determine the tag bits based on the book's answer?

The answer shows the following:

We know that 16 KiB is 4096 (212) words. With a block size of 4 words (22), there are 1024 (210) blocks. Each block has 4 $\times$ 32 or 128 bits of data plus a tag, which is 32 $ - $ 10 $ - $ 2 $ - $ 2 bits [emphasis added].

I see that 32 is the assumed address size (in bits); 10 is the index (log2 of 1024); and 2 bits are the offset; however, what are the other 2 bits subtracted from 32?

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Since Hennessy & Patterson uses MIPS architecture as the basis for all its examples, we can assume that this example is no exception. MIPS is byte addressable. Hence a byte offset of 2 bits (to address the four bytes in the 32-bit word size) need to be included in the 32 bit address.

These 2 bits occupy the least significant two bits of the 32 bit address's binary representation. Hope that helps!

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