# How does the OS detect B&B violation from hardware?

After reading about Base & Bounds memory protection mechanism from Stanford CS140 lecture notes, I understood from the explanation below that there is an integrated circuit performing B&B checks somewhere in the CPU (correct me if I'm wrong):

On each memory reference, virtual address is compared to the bound register, then added to the base register to produce a physical address. A bound violation results in a trap to the operating system.

However I didn't find any information about how the OS detects such violation from the hardware in order to handle the exception.

Does anyone have any idea?

• "That means the CPU then switches to privilege mode and calls the OS exception handler" Does this mean that the OS gets interrupted and points to the exception interrupt request code within IVT? – Kais Jan 13 '18 at 15:14