After reading about Base & Bounds memory protection mechanism from Stanford CS140 lecture notes, I understood from the explanation below that there is an integrated circuit performing B&B checks somewhere in the CPU (correct me if I'm wrong):

On each memory reference, virtual address is compared to the bound register, then added to the base register to produce a physical address. A bound violation results in a trap to the operating system.

However I didn't find any information about how the OS detects such violation from the hardware in order to handle the exception.

Does anyone have any idea?


When an invalid access is detected, the #BR exception is triggered, the CPU will switch to privilege mode and load the corresponding vector (Bounds range exceeded) from the IVT. The CPU also pushes the faulty EIP (as well as other things) to the kernel stack and updates the BNDSTATUS register to describe the fault.

Note: the #BR exception saves other purposes as well because Base & Bound works like paging: there is a 2-level hierarchy to store B&B values (since the CPU can only store 4 of them in registers), so it works a bit like a TLB but for B&B.

  • $\begingroup$ "is some registers": maybe you are meaning 'in'? $\endgroup$ – user6039980 Jan 13 '18 at 14:56
  • $\begingroup$ "That means the CPU then switches to privilege mode and calls the OS exception handler" Does this mean that the OS gets interrupted and points to the exception interrupt request code within IVT? $\endgroup$ – user6039980 Jan 13 '18 at 15:14
  • $\begingroup$ What are called those registers? $\endgroup$ – user6039980 Jan 13 '18 at 15:15
  • $\begingroup$ I updated my answer with more details. $\endgroup$ – Amaury Pouly Jan 13 '18 at 16:45

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