The OR and AND operations are 2-in 1-out.
An Adder is either 3-in 2-out (shown in your diagram) or 2-in 2-out (not shown). In part, because an Adder has 3 ins and 2 outs, it is composed of more underlying gates than AND and OR.
(But to be clear, it does not require new kinds of gates, the existing AND and XOR, OR, NOT gates, or the negating ones NAND, etc.. suffice.)
If we add two 16-bit numbers (not necessarily on a computer, but speaking mathematically) we get a 17-bit answer. (That we often send that answer back to 16 bits is to risk errors in our systems; and the potential for these errors require mitigation techniques, but that is off topic to this question.)
Think of base ten. In the general case, Two one-digit numbers add up to one two-digit number (though the upper digit may be zero). If we're doing long addition, we carry from one column to the next (going left). That carry going in means we're now adding 3 digits together, and the result is one digit along with a possible carry for the next column. That's why adders sometimes take 3 inputs and other times 2 inputs. The 2-input is for the least-significant-digit, whereas the 3-input is for the rest.
The last column has a carry out that is not used further, but just part of the result. This is why we get one more digit than have the inputs.
In binary the maximum inputs would be a=1, b=1, and CarryIn=1. That adds to 3 (decimal) and 3 is represented as 11 in binary. The first of those one's (from 11 in binary) is the CarryOut and the second pf those one's is the Result in your diagram.