I'm having some issues understanding what happens on a context switch with the physical register file in an out-of-order CPU that implements context switching. Suppose that a CPU consists of 4 hardware thread contexts and that the ISA consists of 32 architectural registers. Does the physical register file get overwritten when a context switch occurs, or do the 4 hardware thread contexts compete on the use of physical registers, for faster context switches (because they don't need to be overwritten)?
More concrete: "Does a CPU with 4 hardware thread contexts and an ISA consisting of 32 architectural registers and 96 physical registers in total make sense?"
I am not expert about hardware threading but I know two different ways to achieve it with potentially different answers:
Architectures where the CPU executes one thread at a time but switches on some events (quantum expire, cache miss, switch instruction, ...). In that case, the CPU only really needs 32 registers and on a context switch it can store/load them from either physical registers or memory. Another option is to to register renaming (see below)
Architectures where the CPU really executes the thread in parallel: this can be a Barrel processor that switches on every cycle, or a more complicated out-of-order architecture like Hyper-threading. In both cases, the CPU really needs 128 registers. The way it is usually implemented is that registers are renamed: the CPU has registers 0-95, and register i of thread j is renamed to 4*i+j (for example register 2 of thread 3 is renamed 3*32+2=98). The advantage of doing that is that the pipeline and functional units scheduling and all becomes almost thread agnostic.