Reading up on TTA CPU designs and the wikipedia article states that

Some TTA implementations support conditional execution.

The trick to make an TTA ISA Turing-complete with an unconditional MOV instruction escapes me. Can anyone explain how that would work? (or share some resources where it is explained)

  • $\begingroup$ github.com/xoreaxeaxeax/movfuscator $\endgroup$ – sudhackar Feb 4 '18 at 9:19
  • $\begingroup$ Looks very cool, but I have trouble finding the answer in it... $\endgroup$ – obiwanjacobi Feb 4 '18 at 11:04
  • $\begingroup$ So, it cannot be done, or this niche topic is uninteresting? $\endgroup$ – obiwanjacobi Feb 21 '18 at 17:25
  • $\begingroup$ cl.cam.ac.uk/%7Esd601/papers/mov.pdf is the paper that says mov is turing complete. Check out the repo I linked and the additional documents. $\endgroup$ – sudhackar Feb 22 '18 at 15:41
  • $\begingroup$ So you use the values as an indirect memory addressing index and the set (mov) known but different values into them. That is so lame and corrupts your memory. $\endgroup$ – obiwanjacobi Feb 23 '18 at 7:11

For a CPU designed to use a TTA (Transport Triggered Architecture), one way to implement conditional branch could use a couple of addresses for these purposes:

  • BRANCH_ADDRESS: stores the location to branch to
  • BRANCH_ZERO: Sets PC to BRANCH_ADDRESS when value written is 0. Otherwise does nothing.

This could be used to implement a 'branch-if-zero'. You could also add additional addresses that implement other branch modes, including those ithat hook into flags/state of other components hooked up to the TTA CPU, such as an ALU.


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