# Latency and Throughput Bounds

Say that I have a superscalar processor and I am given the latency, issue and capacity (in clock cycles) for different instructions.

What is the general formula for latency bound and throughput bound? (I will convert to cost per instruction and billion instructions per second)

This field seems to be too niche to find information online.

In other words, how can I find the latency bound and throughput bound for fdiv

     Latency   Issue  Capacity
fdiv    L        I       C


where L is the number of cycles for the fdiv latency, I for issue and C for capacity?

Would $\text{latency bound} = {L \over I} \times C$ and $\text{throughput bound} = {L \over C}$?

This is not the homework problem, but a "required" definition in order to be able to start it.