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For an Instruction fetch cycle we have the flowing registers in a CPU.

  1. Memory Address Register (MAR)

  2. Memory Buffer Register (MBR)

  3. Program Counter (PC)

  4. Instruction Register (IR):

  5. Accumulator Register:

  6. Stack Control Register:

  7. Flag Register:

Out of these I have come to know that PC and IR registers belong to control unit and accumulator belong to ALU but I do not know about rest of the registers. Either they also belong to CU or ALU or they exist separately not as apart of ALU OR CU ?

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They are part of the memory interface between the CPU and the memory subsystem.

The MAR (Memory Address Register) is closely associated with the memory address bus, and the MBR (Memory Buffer Register) is closely associated with the memory data bus.

Some CPUs choose to connect their general purpose registers more or less directly to those busses, thus eliminating these specialized registers, but this is not usually the case in accumulator machines that you're describing in your question.

Some CPUs have a secondary ~ALU dedicated to addressing computation (so probably just add and some specific shifts, e.g. by 0, 1, 2, or 4); such a secondary ALU might also work in conjunction with the MAR or in replacement of an MAR.

On some processors, the CU will have to interleave requests for instructions from memory with requests by the program for data from memory. The instruction address (found in the PC) may first go through the MAR during fetch, or the PC value may be sent directly to the address bus during fetch, depending on the CPU design.

If the processor has a separate instruction cache and data cache, then it has two memory subsystem interfaces. Typically the PC will then serve directly as the MAR for the instruction memory interface rather than creating a second MAR for that.


Note that the MAR, MBR, and the IR are internal registers that are generally not visible to the program or programmer, and so only visible if you're looking inside a particular processor's design.  The same instruction set architecture can be implemented in different ways, and in these alternative implementations, the discussions of the above considerations may vary; this happens in a processor family, like x86.

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To complement Erik Eidt's answer, the Flag Register conceptionally gets input from the ALU and is heavily used by the CU.
("The Memory Interface Registers" typically do not feature in the programming model.)

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  • $\begingroup$ I do not get the connection/restriction to Instruction fetch cycle. $\endgroup$
    – greybeard
    Jan 23 '20 at 12:54

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