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I am confused as to how a 16-bit (or 32, 64) processor can store multiple adjacent bytes at once without supplying multiple addresses

For example say we have (16-bit processor) 0xABCD starting at address 0x0000. For loading, the processor would just supply 0x0000 on the address bus and the way the bytes are laid out physically would produce 0xABCD on the data bus, then the processor would just do some neat bit-shifting to get the correct byte of the word

But for storing a byte, lets say 0xCD at address 0x01, what would the processor do about the other byte? (i.e. what would it do about location 0x00)

Thanks

EDIT: I am asking about big-endian architecures

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For a one-byte read to address 0x01, the CPU can read a 16-bit value and discard half of it.

For a one-byte write to address 0x01, if the memory architecture doesn't support that directly, the CPU needs to read the 16-bit value at 0x00, then replace the second byte with 0xCD, then write a 16-bit value to 0x00.

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These are hardware details that vary, historically a lot, maybe not so much these days. Unless you're designing hardware, or are tweaking software performance at a very low level, it hardly matters.

When the processor presents an address and a fetch/store request, the memory subsystem is a black box that does what's needed. A 1-byte store might or might not involve fetching a larger number of bytes, slotting the stored bits into the required position, and then storing all the modified data back to the original place. Fetching or storing multiple bytes to an unaligned address might require more memory operations than to an aligned address.

Some architectures even forbade the kind of operations you're thinking of, where it wouldn't be "easy" for the hardware to do what is required.

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