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Hi! I faced a problem with calculating IPC.

I can tell the answers were derived from IPC=instruction/number of cycles.

But I have no idea why it has to be calculated that way.

Just to understand the meaning of IPC, it seems like how many instruction can one cycle(clock) handle which obviously is not the case for this question..

Hope to get some helpful answers from here!

Thank you in advance!

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The computation of instructions per cycles is a measure of the performance of an architecture, and, a basis of comparison all other things being equal.  IPC can be used to compare two designs for the same instruction set architecture, as in the question you're asking comparing two design alternatives for a MIPS architecture.

Or, IPC can be used to compare vastly different designs (like CISC vs. RISC).  If the processor can execute one instruction per cycle, then the IPC=1. Especially processors in the 1970's were usually were microcoded, and instructions completed in a variable number of cycles, like some in 2 cycles or some instructions in 4.  So, for these machines IPC < 1.  Some processors using VLIW or EPIC or other architectural designs might complete several instructions in one cycle.

A MIPS processor attempts to execute one instruction per cycle using its pipelined design.  However, certain conditions cause it to stall:

  • waiting for a result that isn't ready, like multiply or divide
  • waiting for a cache miss to resolve

Other times, it does work, but the work must be thrown away — this is the case of the branch instruction.  More specifically, the issue of how soon the processor can get back onto the right instruction stream.

Let's look more closely at the pipeline for the question you're asking about: Here the code sequence is

<x>
B trg
<a>
<b>
<c>

In the following, @trg represents the instruction at the target of the branch, and this is the proper instruction to execute immediately after the branch.

    IF       ID      EX     MEM      WB 
-1  <x>                                 
0   B trg   <x>                         
1   <a>     B trg   <x>                 
2   <b>     <a>     B trg   <x>         
3   <c>     <b>     <a>     B trg   <x> <--- if the branch executes here in the MEM stage, then <a>,<b><c> are unwanted and have to be discarded.
4   @trg    <c>     <b>     <a>     B   
5           @trg    <c>     <b>     <a> 
6                   @trg    <c>     <b> 
7                           @trg    <c> 
8                                   @trg    

The above shows the branch executing in the MEM stage.  Thus, the fetches the processor did for < a >, < b >, and < c > are invalid and have to be discarded.  Three cycles are lost or wasted.

    IF       ID      EX     MEM      WB 
-1  <x>                                 
0   B trg   <x>                         
1   <a>     B trg   <x>                 <--- if the branch executes here in the ID stage, then only <a> is lost
2   @trg    <a>     B trg   <x>         
3             @trg  <a>     B trg   <x> 
4                   @trg    <a>     B   
5                           @trg    <a> 
6                                   @trg

Since the ID stage is 2 stages earlier, this processor has a larger IPC.  We can use the IPC to ascertain exactly how much faster this design would be, and this demonstrates the value of the IPC definition.


(There is term in sailing and yachting called Velocity Made Good, VMG — the idea is that even though you're going a certain speed (in sailing: knots, in computing: cycles per second aka hertz), only some of that speed goes to useful work being done (in sailing: reaching the finish line, in computing: completing instructions from the program).  VMG for a processor would be instructions / hertz.  So, compared to VMG which includes a time component, IPC factors out the time component.)

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