I am trying to understand basic concepts such as MIPS rate, frequency, CPI etc.

But I am having some trouble understanding the details. For example suppose a processor designer builds a processor with frequncy 200 kHz and furthermore let's suppose that the processor has MIPS of 0.2. In what ways can that design be accomplished?

What I am thinking is: 200kHz = 200 * 1000 = 200000Hz so that's 200K pulses per second. Based on this if I calculate the CPI by the formula:

$$MIPS = \frac{f}{CPI \times 10^6}$$

$$CPI = \frac{f}{10^6 \times MIPS}$$

$$CPI = 1$$

Now, this is the number of the overall cycles per instruction.

Here are my questions:

  • What other consideriations that the designer must consider to design such a processor?

  • Doesn't a CPI of 1 mean that the CPU literally executes all instructions in a single clock cycle, I am guessing you can't execute an instruction in less than 1 clock cycle so to get that overall result they must all take 1 clock cycle so the overall CPI is 1. How feasible is this?


  • $\begingroup$ Any modern processor will be able to execute more than one instruction simultaneously. So CPI = 1 or CPI < 1 is quite possible. But it's not only a matter of processor, but also a matter of the actual code. $\endgroup$ – gnasher729 Apr 23 '18 at 22:13
  • $\begingroup$ @gnasher729 By simultaneously I am guessing you talk of multi-core CPU which the modern ones are and therefore they(it) can execute 2 instructions simultaneously one at each core and achieve CPI <= 1. Can a single-core processor have CPI<=1? $\endgroup$ – CupOfCoffee Apr 23 '18 at 22:40
  • $\begingroup$ @CupOfCoffee : The term is "superscalar" (ask Wikipedia) : Since the '90s, fast CPUs (such as Intel/AMD x86 or ARMs in phones) are designed to be able to execute more than one instruction per cycle, practically between 2 and 6. That include decoding, dispatching, execute, retire more than one instruction per cycle. There are many constraints, such as dependencies between instructions, some instructions are complex (divisions for example), or memory latency and cache misses, which can raise the average CPI. $\endgroup$ – TEMLIB Apr 23 '18 at 23:39

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