How is an ISA written? Is it just a bunch of binary combination encoding presets that is stored onto RAM? In other words, is it basically a “dictionary” of binary being defined as an instruction ‘word’ such as add? Once the instruction ‘word’ is recognized, does that mean an action is defined/assigned in that ‘word’? For example, let’s say 101010 is some encoding in x86 that = add, but then add = 111000, which is some electrical signal of add, then 111000 = action, then action = using ALU take register 1 and 2 and adds them? Also, is storing the result part of that action of add or is it it’s own separate thing? My guess is that it’s part of the action of add.

From my understanding and using my analogy of a dictionary , I’ve thought about it in this way. Instead of thinking of it as one complicated dictionary with meanings on meanings on meanings, I’ve split it into two dictionaries: one dictionary for the encoding of your ISA (the opcodes/instruction format) and the other dictionary for what that encoding means, meaning it’s actions. There’s a microcontroller unit with a ROM aspect that is the dictionary for my so called “action”, which are the electrical signals that correlate to decoded instruction. Then there’s your ISA, set of instructions, that’s located on your RAM which is a dictionary for the instructions when the opcode being called. Am I correct? Please tell me I am. Follow up, how is the ISA loaded into RAM to begin with? What tells it to do that? Is it the microcontroller unit? Also, how does an ISA even go about naming and defining certain registers to have a certain roles and functionalities? I’m genuinely confused. Is the ISA like an OS where as soon as the computer boots, the instructions get stored into RAM (if so, how?) and these registers immediately recognize their names and roles? I definitely feel like I have some sort of misconceptions and misunderstandings here.

Then there's also the instruction cycle which I learned about separately. It's fetch, decode, execute. What is making it do that? How is the cycle being executed? Is that programmed through the ISA? Is it some kind of hardwired thing at the microarchitecture level? If so, please explain.

Lastly, how exactly does the implementation process of the ISA and microarchitecture work? Do you create the ISA first then implement that onto the microarchitecture level? Or is it created by working hand and hand with each other? By that I mean, does Intel have two teams: one dedicated on creating the ISA and one on creating the design of the microarchitecture(hardware)? If the answer is two separate teams, I do not understand how you can go about creating your digital logic(hardware) efficiently without working close together with the ISA team. Even after creating and finishing their product, how do they implement it with one another? Please help me understand the implementation process :(

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    $\begingroup$ This is a very broad question. Really, I think you need a textbook on computer architecture, because what you're asking us to write as an answer is basically several chapters of that. We'd love to help but you're asking too much. $\endgroup$ – David Richerby Jun 8 '18 at 10:06
  • $\begingroup$ Some of your questions, though, you're over-thinking. What makes the fetch-execute cyle happen? The CPU contains circuits that are specifically designed to do that. They didn't just appear out of thin air -- they were put there by the chip's designers for that exact purpose. $\endgroup$ – David Richerby Jun 8 '18 at 10:09

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