I am studying cache coherence MESI protocol with "intervention" (cache can send to other cache without use the Main Memory).
On my notes I wrote that in case of a processor has a block in M (modified state) and read on the bus a
Write operation done by an other Cpu, the processor sends the block directly to the cache that want to write (intervention) AND to the Main memory and then change the state to I (invalid)
But why it has to send the block even to the main memory? I mean, it could simply send the block to the other cache (and then will be that cache the will send the block to MM in case of an other CPU want so read the block).