I am studying cache coherence MESI protocol with "intervention" (cache can send to other cache without use the Main Memory).

On my notes I wrote that in case of a processor has a block in M (modified state) and read on the bus a Write operation done by an other Cpu, the processor sends the block directly to the cache that want to write (intervention) AND to the Main memory and then change the state to I (invalid)

But why it has to send the block even to the main memory? I mean, it could simply send the block to the other cache (and then will be that cache the will send the block to MM in case of an other CPU want so read the block).

  • $\begingroup$ Can you provide a reference to the protocol. I have come across MESI, MOESI and MESIF. What you are describing sounds like a combination of MOESI and MESIF. $\endgroup$
    – Isu
    Jun 12 '18 at 9:10
  • $\begingroup$ en.m.wikipedia.org/wiki/MESI_protocol, my question is about on write done by an other processor to a block that I have in M state. What happen in case ho intervention? Could I just send the data to the other cache or Have I to send the data also to the MM ? $\endgroup$
    – linofex
    Jun 13 '18 at 16:10
  • $\begingroup$ Refer to Table 1.2. Modified cache block is written to main memory and the cache line is set to invalidate. BTW when I asked for a reference, I was after the "MESI" protocol you were referring, the one with "intervention". Reference you gave is the standard MESI and it does not do any forwarding of modified cache entries. $\endgroup$
    – Isu
    Jun 13 '18 at 16:33
  • $\begingroup$ @Isu thanks for the answer. This behavior happens when the protocol is without intervention , but what happen in the case of intervention $\endgroup$
    – linofex
    Jun 13 '18 at 16:35

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