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When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents to the very next stage, so how does NOPs prevent that from happening?
Also when NOPs are introduced the PC doesn't increment and no fetch occurs? How does that happen?
Inserting NOPs is the stall. It delays execution until the result is ready.
A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to each functional unit to control how it behaves. Including whether to pull in a new instruction.
The decoder checks dependencies between instructions and when it sees it needs to delay it will stop pulling in new instructions until it can start the new one.
More advanced CPUs with out-of-order execution (every non-mobile/non-embedded CPU nowadays) will pull in a few more instructions and only start those that don't need to wait on data. The details of out of order execution is too complex to fully explore in this answer.
