# How does RAMDAC get notified about framebuffer write?

I'm learning computer graphics, and I read this course lecture in order to understand how graphics I/O works under the hood. But the following explanation was not very clear to me:

The values in the framebuffer are converted from a digital (1s and 0s representation, the bits) to an analog signal that goes out to the monitor. A video card’s RAMDAC performs this operation, once per frame. This is done automatically (not controlled by your code), and the conversion can be done while writing to the framebuffer.

How does RAMDAC get notified about the framebuffer write? Is there an IOCTL required from OS? or there is a circuitry somewhere that maps the write to RAMDAC input?

It probably depends on the architecture in general, but bear in mind that the phrase "the conversion can be done while writing to the framebuffer" is quite vague. The important point is that generating the video signal is a hard real-time operation, and the graphics hardware is designed to ensure that it always happens, even if someone is trying to write to the framebuffer at the same time.

There are a few ways this could be achieved. Some possibilities include:

• Reads and writes to the framebuffer might always happen at different times. If you consider a square wave clock, for example, writes could happen on the leading edge of the clock signal and reads could happen on the trailing edge. This way, the result of the write is always available when the read occurs.
• If there is contention between a read and a write, the write could stall or be buffered somewhere.
• Reads from the framebuffer to generate the video signal could be buffered in a FIFO or something like that. If a write occurs, it could be allowed to happen as long as the FIFO hasn't drained.

It's possible that there could (as you say) be some kind of bypass circuitry, similar to forwarding logic in CPUs. The input to the RAMDAC could be a multiplexer, with one input directly from framebuffer RAM and another from somewhere else.

I think this is unlikely, because it seems excessive to implement extra circuitry just to ensure that a write that is happening right now appears on this frame. A buffer or stall seems much more likely.

The "once per frame" part is totally wrong.

Traditionally, a "RAMDAC" combines a little bit of RAM and three Digital to Analog Converters, for three colours. The RAM part is used for indexed colours mode, for example in the old VGA 320x200x256c mode, each colour is indexed from a table, sometimes named "palette". For "truecolor" modes, 16 or 24bits, the RAM part is bypassed and pixel colours are directly stored in the framebuffer.

To generate a picture, the framebuffer is continuously read and data (=pixels) are forwarded to the DACs. Imagine a counter which is reset after every frame (typ. 60-80Hz refresh), then incremented for every pixel. With modern high resolution displays, pixel read rate can exceed 200MHz (a different pixel is transmitted on the wire between the computer and the screen every 5 nanosecond, or less).

Nowadays RAMDACs are integrated in the GPU for the VGA output. For digital outputs, HDMI, DisplayPort, there is no analog "DAC", except in the LCD panel itself.

For an example of traditional RAMDACs, when it was a separate chip, look for "Bt485A"