0
$\begingroup$

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?

enter image description here

$\endgroup$
4
$\begingroup$

The typical scenario where this kind of incoherence can occur is when the page table has been changed. In this case, an invalid PTE has become valid; perhaps the area of address space has been allocated, or a page has been swapped in.

"But", I hear you say, "why wasn't the TLB entry flushed when the PTE changed?" Well, it probably was, but the change may have happened on a different core.

The way this is typically handled in a multiprocessing operating system is to perform a "TLB shootdown". The core which changed the PTE issues an inter-processor interrupt (also known as a "crosscall") to any other CPU which may have a copy in its TLB to instruct it to flush.

An inter-processor interrupt is an expensive operation. But, of course, it doesn't need to happen a lot of the time. For example, if the other CPU is not currently using an address space which uses the TLB entry, it can't possibly access the entry until it performs a context switch, so the flush can be delayed until the next time the CPU enters the kernel (say).

But even if the other CPU is using the address space right now, you still don't need to perform a shootdown in this specific case, because the stale TLB entry is invalid. Attempting to access it will cause a page fault, so any attempt to use the stale TLB entry will be resolved by the page fault handler. And if that never happens, you've saved yourself a costly inter-processor interrupt.

$\endgroup$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.