1
$\begingroup$

From my homework:

Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is run a program that is saved from 1000H to 10FFH address and repeated 20 times. Suppose the cache memory is empty before running this code. Show the addressing architecture of this cache memory and also calculate the miss rate of the cache memory for sample code.

I believe that I have the first part correct.

Offset = 5 bits

Index = 2 bits

Tag = 9 bits

Is the offset correct? I am not sure if it supposed to be 5 or 3. Does the instruction and operand being 32 bits mean that data is pulled from cache 4 bytes at a time?

The sample code portion is confusing to me. From a discussion with the teacher:

Sample code refers to the program stored at 0x1000-0x10FF as described in the problem(i.e the memory blocks the cache will have to pull for the cpu)

How do I calculate the miss rate from this?

$\endgroup$

0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Browse other questions tagged or ask your own question.