# Difficulty understanding the faster multiplication hardware

This is a picture of faster multiplication hardware taken from Computer Organization and Design (5th Edition). I'm having some difficulty understanding it. I was trying to simulate this for a test multiplication of : 1011 x 101. Firstly, P0 is simply the LSB of the (Mplier0 * Mcand) which gives P0 = 1 The two operands of the upper rightmost adder would be then, 1011 (Mplier0 * Mcand) and 0000 (Mplier1 * Mcand) which would produce the result 1011 with P1 = 1. This 1011 would then be one of the inputs of the second stage adder. The other input of the second stage/level adder would come from the upper 2nd rightmost adder. Which gives 1011 (Mplier2 * Mcand) + 0000 (Mplier3 * Mcand) = 1011. So the two inputs of the second stage adder are both 1011. Finally the output of this second stage adder will be 1011 + 1011 = 10110. The penultimate result is 1011011. But the correct answer is 110111. What am I doing wrong here?

• You're focusing too much on the details. Instead of looking at the diagram, try coming up with the circuit on your own. It's more important to understand the idea than the exact implementation details. – Yuval Filmus Jul 28 '18 at 21:59
• I've looked at it for a long time. Tried to come up with my own implementation but failed. Any help would be appreciated. @YuvalFilmus – Robur_131 Jul 28 '18 at 22:39
• Another question came to my mind that do the adders need to be wider as we go down ? Because my product is 64 bits but all the adders are 32 bits. Wouldn't it cause some problems? – Robur_131 Jul 28 '18 at 22:40
• Okay, I seem to have understood it. The LSB goes to P_n at each step and the rest goes to adder input. – Robur_131 Jul 28 '18 at 22:49