Pipelining without operand forwarding

Question

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l)

One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$):

Here, we assume a RISC processor. The text says:

For consistency with the rest of the text, we use MIPS64, the 64-bit version of the MIPS instruction set. The extended 64-bit instructions are generally designated by having a D on the start or end of the mnemonic. For example DADD is the 64-bit version of an add instruction, while LD is the 64-bit version of a load instruction.

Here F,D,E,M and W refer to the five stages in a pipeline i.e Instruction Fetch, Instruction Decode, Execution/Effective Address Cycle, Memory Access and Write-Back Cycle.

Is the give solution correct?

My attempt was:

Here, in the second instruction i.e DADDI , there are only two stalls. But since there is no operand forwarding, I believe the contents of the register be available after they've been written into the register file and so, there should be three stalls.

From what I could understand in this solution, the value from the register file is available after the M stage, before it is written. Is that possible?

Answer 1

You would be correct, however the question specifically states:

Assume registers can be written and read in the same cycle, during writeback

This means that in cycle 5, 'W' and 'D' are allowed to occur simultaneously, and there must be some sort of implicit forwarding between the two. In light of these assumptions, 2 stalls is right, not 3.