Basically no, but what does happen differs.
Typical educational material doesn't forward into the MEM stage, even though indeed it could do that, and may show a hazard detection unit (which makes the acronym MIPS a bit of a lie). For example from Patterson & Hennessy - Computer Organization and Design 4th edition (MIPS ver.):
Any load-use hazard is handled by inserting a bubble (the Hazard detection unit at the top does that), even
lw into the data-operand of
sw (we cannot forward into the address operand since it needs to go through the ALU), for which there could be a separate forwarding unit but there just isn't. In this case, the example code would have a bubble inserted between the load and the store.
In the real MIPS I ISA, implemented by early hardware such as R2000 and R3000, the load-use hazard is exposed (leading to a "load delay slot"), as is the control hazard of a branch ("branch delay slot"). This simplified the hardware as there was no need for a hazard detection unit (nor second forwarding unit). It doesn't mean that it runs code incorrectly by the way, rather, the code would be incorrect if it doesn't take those things into account: the ISA is "correct by definition" even if it is odd.
These features are not very friendly to students.. and actually also not to more advanced implementations of the ISA. For example, if you have a cache then the latency of a load is variable, delay slots don't solve that, the control logic has to deal with it. MIPS II removed the load delay slot, but the branch delay slots stayed in some form until they were removed quite recently in MIPS32/MIPS64 Release 6 (2014).