Data hazard or forward in MIPS SW after LW in this case?

Question

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes.

Look at this piece of code:

lw $6, -16($6)
sw $6, -16($5)

So the sw wants the data that comes from the MEM read and it wants it just for the MEM write. So we can use a bypass to forward the output of the MEM to the input of the MEM (in the data write input) and this is solving the hazard without a bubble (nop).

Is it implemented into the MIPS core and if not, what will it do?

Answer 1

It is unclear to me if you ask about the "real" MIPS chips, or about the simplified educational version one sees in class.

If you mean the former, then I would guess it does. Well, the CPU probably has way more steps in its pipeline, caches, and tons of other fancy machinery, but I think it is safe to assume that any valid code will run correctly on it.

As for the simplified 5-step pipelined MIPS: again, it depends on which version you refer to. Certain books have load-hazard circuits which are supposed to take care of most situations. But if you have a drawing of the circuits I guess you will be able to tell by yourself if forwarding units exist or not.

The moral is - the MIPS must run correctly any piece of code. If the code you present causes a hazard, then the MIPS hardware must$^*$ deal with it somehow. In most classes that teach MIPS they leave some parts off so maybe you saw a partial design that doesn't take care of it. If you have a specific version in hand, you can check.

$^*$Well, if the MIPS hardware doesn't take care of this, then the programmer (i.e., the compiler) must take care of it. This is less desirable.

Answer 2

Basically no, but what does happen differs.

Typical educational material doesn't forward into the MEM stage, even though indeed it could do that, and may show a hazard detection unit (which makes the acronym MIPS a bit of a lie). For example from Patternson & Hennessy - Computer Organization and Design 4th edition (MIPS ver.):

Any load-use hazard is handled by inserting a bubble (the Hazard detection unit at the top does that), even lw into the data-operand of sw (we cannot forward into the address operand since it needs to go through the ALU), for which there could be a separate forwarding unit but there just isn't. In this case, the example code would have a bubble inserted between the load and the store.

In the real MIPS I ISA, implemented by early hardware such as R2000 and R3000, the load-use hazard is exposed (leading to a "load delay slot"), as is the control hazard of a branch ("branch delay slot"). This simplified the hardware as there was no need for a hazard detection unit (nor second forwarding unit). It doesn't mean that it runs code incorrectly by the way, rather, the code would be incorrect if it doesn't take those things into account: the ISA is "correct by definition" even if it is odd.

These features are not very friendly to students.. and actually also not to more advanced implementations of the ISA. For example, if you have a cache then the latency of a load is variable, delay slots don't solve that, the control logic has to deal with it. MIPS II removed the load delay slot, but the branch delay slots stayed in some form until they were removed quite recently in MIPS32/MIPS64 Release 6 (2014).