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What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This could also happen if the CPU is in paging mode and the page table maps the virtual address to a physical address that is out of range. A physical address is out of range iff that address is not served by any of the plugged RAM chips.

Would the CPU run into an exception and invoke some interrupt service routine? Would the CPU read/write some garbage value?

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The exact response is hardware implementation specific. Typically the memory access will timeout and a hardware exception will be generated. DEC called these Machine Checks, other manufacturers may use different terms. The CPU will follow some interrupt path that will handle the timeout. In normal operation the most common result will be a system crash (again different terms are used, but "Bugcheck" was favored by DEC, "ABEND" is used by others.).

There are some system implementations that don't have a timeout mechanism, in these cases the typical response would be a hang waiting for a response from memory or in a less desirable case, random noise would be read from the data lines.

During boot sequences, the exception handling is sometimes changed so that the system configuration can be discovered. The configuration code may "probe" addresses until it gets an exception in order to find the end of physical memory. Again, this is architecture dependent and not always necessary if the hardware provides some other means of determining the installed memory.

Since you mention ARM specifically, you can read a white paper for ARM memory implementation here: Principles of ARM® Memory Maps This paper has the following recommendation regarding memory accesses: "Unpopulated DRAM partitions must not alias any other addresses, accesses should return bus errors."

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  • $\begingroup$ Thanks. Along the lines of what you pointed out, ARM document also says "DRAM holes (when present) must not alias any other address, including DRAM, and accesses should return a bus error." $\endgroup$ – Abhishek Anand Oct 4 '18 at 16:29

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