I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead..
So, my question is pretty much the same as the one in the question I linked:
I know that in a byte-addressable cache, a byte-offset (usually the LSB of the address) is used to determine which byte to access out of the designated cache block.
But, if the offset allows the selection of 1 byte out of the block, we would need 4 subsequent accesses to the cache in order to access a single word (assuming a word equals 4 bytes), and I somehow doubt that's the way things execute in real time.. Any clarification regarding that will be appreciated, as I didn't find an answer to that in the previous question).

Edit: To clarify my question - I'm trying to understand how can a Byte-Addressable memory output more than 1 Byte at a time.
I'd understand it if the memory Always outputs a whole word, for example, and the byte is then extracted by the CPU according to the requested address by specifying an offset of 0x0 to indicate that it needs 2 bytes - the 1st and 2nd bytes, 0x1 to indicate it needs the 3rd and 4th bytes, 0x00 to indicate it needs only 1 byte - the first byte, 0x01 to extract only the 2nd byte, 0x02 to extract only the 3rd byte, 0x03 to extract only the 4th byte, and specifying no offset at all to tell the CPU "do not extract any specific bytes - process the word as a whole".
That will make for a nice explanation - But I've seen no indication of anything of the sorts while looking at various CPU implementations..

What makes you think that?

If you have a modern high-performance CPU with 256 bit = 32 byte vector registers, then the byte offset determines which group of 1, 2, 4, 8, 16 or 32 consecutive bytes to transfer. Nobody in their right mind would transfer individual bytes. Much too slow.

What will happen and may slow down things a little bit is that if the group of bytes to transfer is not contained in one single cache line, then two accesses are made to two different cache lines. For example, if your cachle lines are 64 bytes and you try to access a 32 bit (four byte) item at byte offset 61, 62 or 63.

• Then the Byte Offset doesn't specify which single-byte to access, but instead determines how many bytes to access at once? Then what happens if I Do need a single byte, which isn't the first byte in the line? How can I tell the cache which of the.. say, 4 bytes, is the relevant byte? Does the cache retrieve all 4 bytes in a case where I need only the 4th byte? Oct 18, 2018 at 15:52
• No, the byte offset specifies which is the first byte to access. Oct 18, 2018 at 22:14
• Then.. Again, if the memory is byte-addressable, doesn't it mean the memory's output is 1 byte long? How can it output more than 1 byte at a time? My question applies to any sort of memory, actually - Not just a cache Oct 24, 2018 at 14:10
• It means the address of any single byte can be processed. And used to return 32 bytes, for example. It’s byte addressable, not byte accessible. Oct 24, 2018 at 17:38

Your whole question is predicated on the belief that byte-addressable means that only bytes can be returned. That's like assuming that, because every page in a book has a number, it's only possible to tell somebody "Please read page 17" and you can't say "Please read pages 17 and 18. That simply isn't true.

It's perfectly possible to build hardware that, when you give it an address $$A$$, returns the byte at that address, and also the bytes at addresses $$A+1$$, $$A+2$$ and $$A+3$$, regardless of whether $$A$$ is a multiple of four. Heck, it's even possible to build hardware that returns the bytes at addresses $$A-4$$, $$A$$, $$A+3$$ and $$A+9$$. It's hard to imagine a use for that, but you could do it. And, although both my examples have returned four bytes, you could build hardware that returned any other number of bytes. Indeed, you could build hardware that returns any computable function of the memory.

how can a Byte-Addressable memory output more than 1 Byte at a time?

By having an arrangement of transistors and wires that does that. Literally, that's all you need.

• But considering that memory has a single output - Its output size has to stay fixed. If it's designed in a way that each call to memory retrieves a single byte, then the output has to be 1 byte long, and cannot produce a larger output unless you add another physical output to it. Besides, it's obvious that your hardware should act according to the way you've designed it - But I've never found a description of an implementation where the cpu extracts a part of the memory's output according to an additional parameter given to it as an input.. Oct 24, 2018 at 15:18
• My question is regarding current implementations of existing hardware, not what can be create with new hardware.. That's what I'm confused about, hope it's clearer that way Oct 24, 2018 at 15:19
• "If it's designed in a way that each call to memory retrieves a single byte, then..." ... then each call to memory retrieves a single byte. But if it's designed another way, ... The fact that one makes the design decision to have byte addressing in no way forces you to also make the design decision to always return a single byte for every memory access. Those are two completely independent features of the design. Oct 24, 2018 at 15:23

Alright, Thanks for the help :) I was still pretty confused, but after talking to a few more people around the globe, I got an answer which left me convinced:

All that's required from memory so we can call it "Byte-Addressable" is that we can access a single byte out of the memory's data. That means - even if the Memory (as a component - RAM for example) isn't byte-addressable by itself (which means that each address contains, for example, 4 bytes of data instead of 1), then the Memory's DATA can still be considered byte-addressable if you implement another mechanism to let you interact with a single byte out of the data retrieved - Even if that mechanism exists in the CPU, and has nothing to do with the memory's hardware on its own. For example:
Say we have a CPU with a Word-Addressable RAM connected to it.
In order to access a single byte, we add a mechanism to our CPU so it ANDs each Word with a Mask, thus masking-out any irrelevant bytes, leaving us with only the desired Byte (If the RAM's output is 4 bytes-long, say, 0x09ABCDEF, and we are only interested in the 4th byte (0xEF), we can AND the output with the Mask 0x00000011, resulting in our desired byte, preceded by 0s (0x000000EF. In case of a signed output, we should Sign-Extend the output, instead of simply masking it).
So, in the above case, thanks to the mechanism we've implemented in our CPU - We are able to access a single byte from memory. A similar mechanism may be implemented in order to Store a single byte in memory, as well.
Then although our RAM is still WORD-Addressable, our MEMORY (the RAM's Data) is Byte-Addressable, thanks to our CPU.
This has caused a lot of confusion for me up until now, as I've assumed Memory to mean the actual hardware memory, and not its stored data.
Hope this answer manages to help anyone else who might be confused because of it :)