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Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

(A)645ns

(B)1050ns

(C)1215ns

(D)1230ns

What I got is

Average Instruction Execution time=100ns(CPU Time)+ 2 Memory Access.

Since, Each memory access may include TLB hit and page fault

So,

Average Memory Access Time=TLB hit rate*(TLB access time+1 Memory reference(150ns))+ TLB Miss*((Page fault rate x Page Fault service time) +(1-page fault rate)*(3 Memory reference because of 2 level paging.))

Since, TLB access time not given, assuming it to be 0.

So, average memory access time=$0.9(150)+0.1*(10^{-4}(8*10^6)+(1-10^{-4})(450))=259.9955ns$

So, Average Instruction Execution Time: $100+2*(259.9955)=619.991ns$

But my answer came to be wrong and it is given 1260ns.

Can somebody help me where I am wrong?

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    $\begingroup$ Read carefully: "the page fault rate is one in every 10,000 instructions". Average instruction time is at least 8ms / 10,000 due to page faults alone. $\endgroup$
    – gnasher729
    Oct 26, 2018 at 20:06
  • $\begingroup$ @gnasher729-I got your point. But do I need to consider page fault, not in TLB miss? $\endgroup$
    – user3767495
    Oct 27, 2018 at 2:28
  • $\begingroup$ @gnasher-Okay so Average instruction execution time=800ns(due to page fault) + $0.9(2*150)(Because\,of\,two\,memory\,accesses\,)+0.1(2*3*150)+100ns(cpu\,time)=1260ns$ $\endgroup$
    – user3767495
    Oct 27, 2018 at 2:39
  • $\begingroup$ Now am I correct? $\endgroup$
    – user3767495
    Oct 27, 2018 at 2:41

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