# Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working with a 5 stages pipeline processor withouth data forwading paths)

So if I have the following code now:

Store R3,R8,off-1


If we've had ADD and Subsract instructions instead of "store" and "load" we'll have data hazard dependences, so we would have to "wait" for the result using No-Op, but in this case; can I start "fetchig" the second instruction while the first one is on "Decode" stage?

I think I'm missing some concepts here, as to where the operand is fetched from and where it gets stored to.

Thank you.

• Either the CPU is very simple and can only perform either a read or a write to memory (or to the cache) without reordering, then there is no additional hazard. If the LOAD can be executed while the store is posted to some write buffer, but not yet in memory, the CPU must check that there is no collision, by comparing the address of loads with the address of pending writes. – TEMLIB Aug 24 at 12:31

Assuming the stages are IF, ID, EX, MEM and WB, I believe the Load instruction cannot be carried out until the value has been written back in the first instruction i.e the WB stage.

This is what happens in the ID stage (from Hennessey-Patterson, Computer Architecture - A Quantitative Approach 4 ed.):

Decode the instruction and read the registers corresponding to register source specifiers from the register file.

Since we have to read the registers in the ID stage, this cannot be done until the WB stage of the previous instruction has been completed as otherwise, it would lead to reading an incorrect value.

EDIT: On further notice, I've realised this might be incorrect. I wrote this answer under the assumption that the Store instruction passes through all the five pipeline stages. However, here, it is mentioned that:

The store instruction stores to memory, so the "write" is performed inside MA.

So it won't have to wait till the WB stage, it can read the value after the MEM stage of the previous instruction.

That being said, more details about the instruction set would be helpful and how exactly are Load and Store defined would be helpful.