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I need to create a HDL which will use logic gates to demonstrate if something is a negative number in two's complement. The input is 8 bits, while the output is 1 bit, and if the input is a negative number then the output should be true, and in any other case, the output should be false.

I've noticed that all the negative numbers in two's complement start with a 1 in their binary notation, i.e the number -8 is written as 1000 in binary, -7 as 1001 and so on until 0, which is when it switches to 0000, 1 being 0001 and so on until +7.

I originally had the idea of using a Not gate for this, but i'm not entirely sure how it would work out. I tried something like:

Not(in=in[1], out=in[2]);
Not(in=in[2], out=in[3]);

etc but it didn't work. I also thought of using an Or gate, as if either of the inputs are true (negative number) then the output would also be true to signify a negative number, but if both of the inputs are false (not negative) then the output would also be false.

Any help?

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    $\begingroup$ just wire the MSB to output ? $\endgroup$ – kelalaka Nov 3 '18 at 18:09
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You miss the obvious solution, just wire the MSB to output.

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