11 questions linked to/from Tag, index and offset of associative cache
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### How to calculate the number of tag, index and offset bits of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
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1 vote
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### Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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### Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
1 vote
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### How to determine the bits of the address used to access the cache?

Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a ...
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### How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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### Direct and Associate Cache - Offset, Index, and Tag

I have two questions: ...
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### Direct-mapping cache question

Say I have the following memory scheme: Data bus: 8 bit Main Memory Store: 256 Byte Cache Store : 32 Byte Block Size : 4 Byte How would I go about listing the assigned bits for tag,...
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### Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
1 vote
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### Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it. Question was this: Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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