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# Questions tagged [cache]

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### Deterministic online caching algorithm competitive ratio lower bound proof

I don't understand the adversary based proof in CLRS for proving lower bound of Ω (k) on competitive ratio of any deterministic online caching algorithm given that ...
• 13
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### How do tag bits help us in 2 Way Set Associative Cache?

Suppose say a computer system uses 16-bit memory addresses. It has a 2K-byte cache organized in a 2-way set associative manner with 64 bytes per cache block. Assume that the size of each memory word ...
28 views

### Page miss in 2Q Cache Replacement

I am studying about 2Q Cache Replacement Policy and i came across this post. They have worked out an example with the following page keys [1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5] and cache memory of 5 ...
42 views

### Problem with cache and memory from university class

In my university class, I received this homework assignment on computer architecture, but I don't know how to solve it. I already know that the correct answer is 0, but I don't understand why. Could ...
78 views

### How to calculate memory bandwidth?

I'm studying for final and currently stuck in the question below. You have an embedded processor. It has its L1 instruction and data cache. No L2 or last level cache are available. Consider the ...
52 views

### Assosciative mapping algorithm

I have been studying the assosciative mapping in a cache.Every line in a cache has a unique address which is made of:the index and the offset bits which give the the cache set and the cache line and ...
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### How to calculate the size of main memory if the cache is 4-way set associative memory, cache memory size is 256KB and number of tag bits is 8

I'm trying to calculate the main memory size, and the only information given is the size of the cache, which is 256 KB, and the number of tag bits, which is 8. Cache is a 4-way set associative memory. ...
102 views

### How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?

In my OS course, the instructor mentioned the following: In UNIX if a parent process creates a new child ("fork") then the child is an exact duplicate of the parent. This means its memory ...
56 views

### Memory Hierarchy Mappings to real world

This article from IBM (link) talks about Memory hierarchy in its actual hardware parts. NUMA While operating systems present memory to the running applications as a unified space, modern large ...
139 views

### Does cache hit time include both time to read a cache and time to write a cache?

For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data ...
2k views

### How to determine tag, index and offset size in a two-way associative cache

How to determine tag, index and offset size in a two-way associative cache with a 1MB two-way set associative cache with 8 byte blocks
1 vote
39 views

### How to decide row / column strides for a loop over a matrix get these cache hit rates?

Given CPU with: L1 cache: 4-ways, block size = 32 bytes , cache size = 64KB , LRU (Cache replacement policy). L2 cache: 2-ways, block size = 32 bytes , cache size = 512KB , LRU (Cache replacement ...
1 vote
137 views

### Resolving a dependency graph with insufficient resources to store all states

A common way to resolve a dependency graph is to compute an execution order, and then execute each stage in turn - storing and fetching the resources as necessary. In this example, when executing ...
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1 vote
1k views

### RAM access time vs cycle time

About Random Access Memory (SRAM and DRAM), if multiple read or write operation take place, many books calculate the average access time of those operations. Given the definition of access time, I ...
• 367
162 views

### How does software prefetching work with in order processors?

From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching: ...
124 views

### Average Access time in caches

I know that the average access time for systems with level 1 caches is: Average Access Time = Hit time + (Miss Rate x Miss Penalty) How can this be generalized for n level caches?
1 vote
2k views

### How to determine the bits of the address used to access the cache?

Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a ...
• 213
296 views

### Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
148 views

### How do I compute the address of the next element?

I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
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1 vote
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### Optimal order to traverse a grid with caching

Let's say I want to evaluate a two-argument function using all possible combinations of elements from sets A and B as arguments. For example, if the function is addition, we get this grid: ...
• 111
118 views

### Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
• 219
4k views

### What does "associative" exactly mean in "n-way set-associative cache"?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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124 views

### I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
125 views

### how to deal with mismatched tag bits in cache

I was reading a textbook which describe general organization of cache as: Then an exercise is, given m=32, C = 1024, ...
• 135
573 views

### Is address bus size same as physical address size and is that the same as word size?

I am having some confusion between address bus size, physical address size and word size however (I do understand that unit of memory access is word and when word size is one byte then it's known as ...
• 219
117 views

### Tag storage when using HBM as an L4 cache

I'm reading through Computer Architecture: A Quantitative Approach, Sixth Edition, and I'm trying to understand the issues surrounding tag storage in using HBM as an L4 cache. The primary concern ...
1 vote
214 views

### Source code or detailed explanation of "WKS" virtual memory compression algorithm?

I've been trying to find information on various program data virtual memory compression algorithms that are in the "WK" family of algorithms. So far, I've been successful with the "WKdm" compression ...
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### How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
391 views

### How to Calculate Clock Rate for Processor?

Please can anyone help me to solve the following question, I have no idea to solve that 👀.
37 views

### 64 byte cache block and memory overhead for cachline with 7 states (3 bits)

I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead: The cache line has 7 states (3 bits): unowned, shared, exclusive, ...
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822 views

### How does a TLB lookup compare all keys simultaneously?

I am reading OS Concepts dinosaur book which says, "Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared ...
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### Can a 2-way set associative mapping have just one set?

Though unintuitive, can a 2-way set associative mapping have only one set. For e.g., Cache size 8 bytes, block size 4 bytes and main memory size as 16 bytes. Here the number of cache lines are 2 and ...
1k views

### Direct and Associate Cache - Offset, Index, and Tag

I have two questions: ...
1 vote
75 views

### Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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5k views

I am trying to understand the difference between byte addressing and word addressing. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The ...
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### Why do computers keep old cache?

I cleaned up my computer and found 50GB of old cache on it and it made me wonder, why do computers keep old cache files?
1 vote
75 views

### design cache system using queuing theory

If we have data from a random population, a 3d histogram of throughput and current cache size of DRAM (intersection of a IOPS & a cache size will have a count). How can one use queuing theory to ...
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1 vote
135 views

### Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it. Question was this: Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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