Questions tagged [caching]

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Doubts on Virtually Indexed,Physically tagged Cache

I tried referring a few material (videos on youtube and this link as well), but I still couldn't wrap my head around the concept. My (brief) understanding of the Virtually addressed, Physically ...
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What is the accepted term for the “stale-while-revalidate” cache strategy?

I was trying to look for docs and libraries about a cache akin to RFC 5861 where objects can be in three age states, fresh and expired (as usual), and a third where it can be returned immediately (as ...
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47 views

Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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cache Hit rate and miss rate calculation one-way associative

I have this problem: A program that calculates the sum of 128x128 matrix of 32-bit integers (by rows). I have one-way cache that has 8 sets with block size of 64 bytes, considering only the access to ...
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Problem regarding caching. Block offset, Set index and Tag

I am currently reviewing for my exam in computer architecture. I've run into a question in the old exam sets that I can't really figure out. The question is regarding caches, more specifically block ...
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1answer
414 views

Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
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13 views

Associative cache finding the tag and word number

An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes. I'm unsure how to find ...
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207 views

Set associative cache calculations

I came across following problem: Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit ...
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1answer
44 views

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
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354 views

Determine the main memory size using cache line and cache size

Assume a computer architecture with 32 bit address.The system has been designed with 1MB cache which comes with 64KB cache line(cache block size). 1.What is the maximum main memory capacity this ...
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1answer
2k views

Calculating Tag Bits in a Direct-Mapped Cache

The following comes from Patterson & Hennessy Computer Org. and Design (5th ed., p. 390): How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, ...
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2answers
47 views

Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
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1answer
74 views

What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
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1answer
55 views

Inline caching in not object oriented languages

I've been recently studying inline caching as a technique to optimize method dispatch in object oriented languages. Basically, the idea is that one can remember what was previously dispatched and ...