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Questions tagged [caching]

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6 votes
1 answer

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
nj2237's user avatar
  • 163
4 votes
1 answer

Inline caching in not object oriented languages

I've been recently studying inline caching as a technique to optimize method dispatch in object oriented languages. Basically, the idea is that one can remember what was previously dispatched and ...
user1868607's user avatar
  • 2,194
4 votes
0 answers

What is the accepted term for the "stale-while-revalidate" cache strategy?

I was trying to look for docs and libraries about a cache akin to RFC 5861 where objects can be in three age states, fresh and expired (as usual), and a third where it can be returned immediately (as ...
Nick T's user avatar
  • 141
2 votes
2 answers

Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
Fady's user avatar
  • 33
2 votes
1 answer

What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
hexpheus's user avatar
  • 133
1 vote
1 answer

Is reading contiguous pages (let's say 4KB) any faster than reading non-contiguous pages on SSDs?

I'm working my way on a problem which requires me to store elements in fixed 4KB-sized pages on an SSD. Each page is requested once for some computation on its elements, and then the CPU requests for ...
Shikhar Jaiswal's user avatar
1 vote
2 answers

Dynamic selection of cache replacement policy

There are some different cache replacement policies could be implemented in CPU. As far as I know, ones have better hit ratio on specific type of code than others, but if that type changes (for ...
RedMurloc's user avatar
1 vote
0 answers

Doubts on Virtually Indexed,Physically tagged Cache

I tried referring a few material (videos on youtube and this link as well), but I still couldn't wrap my head around the concept. My (brief) understanding of the Virtually addressed, Physically ...
mahesh Rao's user avatar
1 vote
0 answers

Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
KGhatak's user avatar
  • 229
1 vote
0 answers

Problem regarding caching. Block offset, Set index and Tag

I am currently reviewing for my exam in computer architecture. I've run into a question in the old exam sets that I can't really figure out. The question is regarding caches, more specifically block ...
Magnus Lund's user avatar
0 votes
1 answer

What is the hit rate of the cache when executing this code?

C++ code: int main() { short int arr[4][4]; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { arr[i][j] = i+j; } } return 0; } Is there ...
Luke's user avatar
  • 1
0 votes
1 answer

Are Paging and page cache the same in Operating system?

I was looking at paging in OS. It seems like there are two concepts with the same name but with different features, and I wanted to be clear about those, Paging and page cache. Before I thought paging ...
sy choi's user avatar
0 votes
0 answers

Deterministic online caching algorithm competitive ratio lower bound proof

I don't understand the adversary based proof in CLRS for proving lower bound of Ω (k) on competitive ratio of any deterministic online caching algorithm given that ...
jam's user avatar
  • 13
0 votes
0 answers

Determine the main memory size using cache line and cache size

Assume a computer architecture with 32 bit address.The system has been designed with 1MB cache which comes with 64KB cache line(cache block size). 1.What is the maximum main memory capacity this ...
Kalana Mihiranga's user avatar
0 votes
1 answer

Calculating Tag Bits in a Direct-Mapped Cache

The following comes from Patterson & Hennessy Computer Org. and Design (5th ed., p. 390): How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, ...
Anton Rasmussen's user avatar
-1 votes
1 answer

Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
schererdavid's user avatar