Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
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compute cache miss rate by given code
I have been trying to solve questions like this before but I have stumbled in difficulty to track the the space of the cache.
so there is an example of a question like this:
Given the code:
...
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Is the executable always loaded to the same place in the text segment?
I am reading a book about data architecture, and I am wondering about the text segment and the memory adresses.
In one example(assembly using ARM) where the code was compiled there were adresses to ...
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Reference/notes for introduction to (von Neumann) architecture
I am interested in understanding what we mean by a von Neumann architecture and need something at a very introductory level. Does anyone know of any good and readable references or notes that will ...
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What does it mean to have the processor ignore interrupt request line?
I was reading a textbook on COA, it says
If the processor is going to ignore the interrupt request line till the execution of the first instruction of the ISR, how will it know which device to ...
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Page fault question
How many page faults are there in the following accesses of pages in case of FIFO mechanism where page frame size is 8?
$$11,21,23,53,8,7,10,3,3,38,3,37,7$$
Soln: This question appeared in one of my ...
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Are really only ~1% of the physical CPU space used for computing
In a Talk by Herb Sutter C++ and Beyond 2012: Herb Sutter - atomic Weapons 1 of 2 at 46:30 the point is made that only around 15% of the physical space (or the transistors) on a CPU do actual ...
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How do we run programs which are bigger than RAM itself
I know that whenever click on .exe, it will be moved into RAM so cpu can execute machine code line by line. But what if .exe is bigger than RAM?
for eg: I play games which take up more space than my ...
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5-stage pipeline CPI
Assuming processor with 5-stage pipeline (Base CPI=1.0). Data hazards cause average penalty of 1 cycle for floating point operations. Int ops run at max throughput. Predict-branch-not-taken technique ...
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Belt-based mechanical computers
I've seen a lot of mechanical computers based on gears and rigid rods, but none so far that consequently use belts (not chains) for transmission of information.
Belts allow for easy negation (by ...
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Resources to learn about the fundamentals of computers? [duplicate]
I have been wanting to learn more about how computers work. Getting way ahead of myself, but as in would it be possible to build a computer from scratch by myself? I mean build the individual parts ...
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Why do we rely on computers in critical fields?
I assume that computers make many mistakes (like errors, bugs, glitches, etc.), which can be observed from the amount of questions asked everyday on different communities (like Stack Overflow) showing ...
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How many CPU cores are there in the world?
I have read some articles about how much total storage capacity there is in the world (eg. https://www.quora.com/Whats-the-worlds-total-data-storage-capacity), and I wondered how many CPU cores are ...
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which devices use parity checking?
I've just started learning computer architectures and I'm having trouble understanding where these are used.
I know that parity checking is testing for accurate data transmission between nodes in a ...
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What kinds of operations do modern GPU (Ampere architecture in particular) perform on FP or INT processing units?
I have a cool algorithm that I've designed while using my laptops M4000M(maxwell) graphics card. I'm looking to get a beefier desktop card to add more oomph to my calculations but find myself in a ...
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What kind of data does L1, L2, L3 cache hold?
I understand that caches are the smallest and fastest memory that is integrated into the CPU. However, what I am confused about is the information that it holds. From what I know, the capabilities of ...
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Is there any video where I can see how different data rates impact daily activities?
I've been learning about data speed and width and the rate of the bus where information is transmitted between components. But I can't see or understand how fast is the transmission.
For example, in ...
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Are GPU's only a fraction of the cost of supercomputers?
According to wikipedia, the Frontier supercomputer is the largest supercomputer in the world, at 1 exaFLOPS, and cost 600 million USD.
I am quite surprised that the largest supercomputer only has 1 ...
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What does interface and peripheral functions mean?
I know that interface means a point where any two things meet and interact, but I can't seem to wrap my head around the term when they use it in computers.
A chipset performs interface and peripheral ...
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2 -bit branch predictor : How we compute the prediction
I have studied the theory on branch predictors, however I am still confused . I can't figure out how we know compute the prediction .
Example:
A system has a BHT with 2-bit predictors initialised at ...
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Finding bits per address in memory
I dont know if this is any important IRL, but I am trying to understand lines below.
4K words of main memory (this implies 12 bits per address).
4M X 16 means the memory is 4M long (4M = $2^2 \times
...
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What can be the topic of my assignment for presentation about overall computing performance?
I have received the below question for presentation. It was random assignment, its not my field. What is this specifically in Computer Architecture?
how CPU and GPU architecture, memory bandwidth/...
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How do I determine how many blocks have been replaced and what the hit ratio is of the following direct-mapped cache?
I have a direct-mapped cache with the following properties:
Address size = 32 bits
Cache block size = 8 words
Entries = 32
So we can see the cache as a 32 by 8 table where the index selects the row ...
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Are all CPU computations done using registers?
From my understanding, a CPU register is a temporary storage or working location built into the CPU itself. The CPU includes some functional units such as the ALU (which is part of the chip, as far as ...
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Does cache hit time include both time to read a cache and time to write a cache?
For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data ...
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Can computers only add?
So recently I've been involved in a discussion and I was told that literally the only thing computer can do is addition. Is that true? What about logic operations? Aren't they performerd by physical ...
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How can this MIPS processor execute one instruction in one cycle?
I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris.
At the end of the section the autor shows this MIPS processor and ...
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What does it mean unambiguously that a number is value 0 up to numerical precision?
I was reading that a quantity $x$ is $0$ upt to numerical precision. What does this statement formally mean -- especially in the context of numerical methods or real computers.
I looked up in google ...
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Difficulty understanding how federation increases cache performance for databases?
I am studying system design for distributed systems and in this page (https://github.com/donnemartin/system-design-primer), one of the following advantages was mentioned for federation for databases ...
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Von Neumann mixed with Havard in modern CPU?
Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
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What is the difference between clock cycle and clock period?
I'm reading Computer Organization and Design Sixth edition by Patterson and they define clock speed as this:
Almost all computers are constructed using a clock that determines when events take place ...
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Performance of CPU with two caches
I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this
Cache L1 ...
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preprocessing or real time for magnification of portions of video
Im new at CS and would like to gather preliminary information to approach an interactive art project.
I want to construct a grid of videos - think about a matrix M = m x n where Mi,j is a video that ...
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How bits translated into text on the screen?
recently i started studying computer science and computer graphics, and one question really haunts me. Mby someone can explain this. How bit patterns become translated into (for example ) text. I know ...
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In Programming data types size are depends upon what?
In Programming there is different data types (int , cahr , bool ,
float ) and they have different sizes (1,2,4,8 .. Bytes) , and the
size of data type are depends upon hardware or architecture of
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Why is C still the fastest? Critique my take
A friend and I were surprised that C still has near-best performance among languages. I thought about why this is, and I wrote up a few paragraphs. I wonder if the friendly folks on CS stack could ...
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Assembly language addressing mode instructions
I am studying assembly language. I feel very difficult in understanding few instruction.
ADD R1,R2,[R3]
ADD R1, R2, R3
What is the difference between these two instructions. I think second instruction ...
user145450
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How are instructions from software sent to digital circuit in cpu?
I am studying computer architecture in my university and there is something that's troubling me. I get the bigger picture of how instructions are executed in the fetch - execute cycle and the complete ...
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If I open & connect with 1 protocol to every port (all 65535) can we still open another protocol socket?
I understand and have googled how TCP & UDP can work simultaneously BUT does this assume there are unused ports to dynamically allocate?
So if all ports are used by TCP can UDP still connect & ...
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Computations in sequential implementation of Y86 instructions
I try to write down computation for Y86 instruction:
...
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Why place of MA in MB then copy from MB to IR rather than going straight from MA to IR
During the fetch stage of the fetch-execute cycle, why are the contents of the cell whose address is in the MA (memory address register) placed in MB (memory buffer) then copied to IR (instruction ...
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Max RAM capacity on modern cpus
I am wondering why modern consumer cpu usually has 128GB memory limit when server cpu supports terabytes. 128GB is really not that much.
Do they really can't handle more RAM? How wide is their address ...
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Why do we not use continuous real quantities to represent continuous numbers
I've just been doing some pondering, and given the fact that computers already operate on fundamentally continuous physical quantities, and then we have to use transistors to turn those real ...
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Calculating memory bandwidth
There's something I'm confused about in calculating the bandwidth. It's defined as number of bytes transferred, and we know that each word is 2 bytes, why are we multiplying 4 words by 4?
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8-bit binary to bcd converter Verilog
We have been given task to write a 8-bit binary to bcd converter Verilog code, using structural code NOT behavioural, is it possible to guide us how can we create 8-bit binary to bcd converter using ...
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Addition in One's Complement
It is my belief that addition in one's complement is done the same way as unsigned addition except that if there is a carry out in the most significant bit then that carry is added to the last ...
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Minimum bitrate of common bus (I/O system) with minimum delay
I have a 32-bit MIPS which is connected to the main memory and a I/O system which is related to memory-mapped I/O, while there is DMA controller. The I/O system has discrete I/O communication lines ...
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Calculate memory size given address and its value
Given the address 00011001111011101111101011011111 and it save a value
0x1FA0CBB7. Calculate the memory size in KB
What i try: the address has 32 bits so the memory size is 2^32 = 4294967296 bytes ...
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Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux
I'm reading CSAPP and couldn't wrap my head around this part:
Summary of what the section says:
Intel Core i7 support a 48-bit virtual address space and 52-bit physical address space.
Core i7 uses a ...
