Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Risc-V extension for dismissible loads

Certain architectures have "dismissible loads" in addition to normal loads: when the load is denied, instead of issuing an exception (leading to a segmentation fault), a default value (e.g., ...
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What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?

I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
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How does virtual memory work when it need to save data in physical memory into disk?

I'm reading a textbook which desribe VM as: a data structure stored in physical memory known as a page table that maps virtual pages to physical pages. The address translation hardware reads the page ...
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Cache Miss and Processor Speed

today in my class my professor mentioned that Cache misses becomes more expensive as the speed of the processor increases But he didn't explain the reason. I ...
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Unsigned/signed boolean

Answer is c). I understand that the expression evaluates to true but what does signed/unsigned have to do with booleans?
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Is there any research on allocating memory across multiple non-contiguous regions?

From my understanding, malloc and-the-like allocate contiguous blocks of memory. It then returns to you the start address of the memory block. This (and other ...
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Course teaching time complexities in real life systems

Having mis-read What course in CS deals with the study of RAM, CPU, Storage? I now wonder what course in CS deals with time and space complexities including GPUs, CPU caches in multiple levels, seek ...
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Is machine epsilon the largest relative error in representing a number as a floating point number?

Is machine epsilon the largest relative error in representing a number as a floating point number? There are so many definitions of machine epsilon. I'm starting to get confused. Isn't the machine ...
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Vectorization vs Asynchronous parallelism

I have taken a course "Programming for Performance" in my college and in the first week of the course, I have come across vectorization and Asynchronous Parallelism. But I am unable to ...
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A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh ...
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Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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memory storage of a program before compiling

Whenever we write code, after compilation the code will be converted to machine language and then stored in the hard disk. But before compiling the code, it is still in the high-level language. How ...
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Booth's algorithm Question : Binary Number Arithmetic (Multiplication)

It's being said booth's algorithm produces the output exactly as normal binary multiplication while reducing the number of operations performed and can be used for both positive and negative numbers ! ...
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How can I mathematically show the largest possible value of a 64-bit double?

I'm a physics student wondering how I can mathematically show the largest possible value of a 64-bit double. I don't want to know just the answer, since that is freely available. The equation I was ...
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Do the newest computers still have ROM?

Now that many computers use UEFI instead of BIOS to boot the computer, and UEFI instructions are usually stored in a hidden hard disk partition, does this mean the newest computers do not need to have ...
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Data Hazards and stalls

I am studying for my exam tomorrow and I am having difficulty in the below code : sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Due ...
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ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
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How can a CPU be busy during DMA access with burst mode transfer

During burst mode in a DMA access, the DMAC has control over the bus for the whole transfer session which includes DATA PREPARATION time as well as DATA transfer time, after the transfer is over, the ...
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Communication between hardware components

We know that each component has different frequencies, but what happens when a fast component directly comunicates with a slow one?
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Universal Turing Machine algorithm

First, I learned this based on these facts: Turing machine (TM) will be define with 7-tuple Notation, $M=\langle Q,G,b,S,d,q_0,F\rangle$. Any computation rules that can use to simulate any possible ...
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How much space an ascii character really takes on a 64 bit word addressable memory?

I know that an ASCII character needs 1 byte of memory for storage, but if a computer uses a 64-bit word addressable memory does it mean that the character actually takes 8 bytes even when only 1 byte ...
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Confused with an Instruction Cycle question

Here's the question The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
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How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
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How to improve the CPI and Speed up factor in CPU-OS simulator?

I am using the CPU-OS simulator by Besim Mustafa(https://www.merlot.org/merlot/viewMaterial.htm?id=476196) and I am studying Pipeline Stages. I have written a simple program and captured the metrics ...
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What bus DIMM (RAM module) uses?

I know there are different types of BUS like PCI, SCSI, ISA etc. What specific type of bus (for address bus and data bus) do a DIMM module use ?
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How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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How is CPU different from GPU?

A central processing unit offers to handle various operations like calculating, watching movies, making presentation etc. While a graphics processing unit is majorly used for the purpose of video ...
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What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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How does computer memory store the file name?

I have this doubt for long time. When i save a notepad file, it takes the memory for the information in the file. let's say, I type 'ABC' in notepad and saved the filename as stack, it shows that the ...
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In a single cycle datapath, do 'decode' and 'operand fetch' occur simultaneously?

After instruction has been fetched, does it go to control unit and register file at the same time or one after the other? For example if the control unit and register read both have 80ps delay, and we'...
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Cache Blocks Direct Mapping

If the main memory address has 18 bits (7 for tag,7 for line and 4 for word) and each word is 8 bits. I found that the main memory capacity is 256-KBytes, total cache lines is 128 line, total cache ...
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Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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Big-endian systems and the smallest memory address

I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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Functions of CPU

What part of the CPU communicates with all the other parts of the processor and makes the processor faster by containing frequently used data or instructions?
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direct-mapped cache

problem is as follow: For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits) Tag: 63-10 Index: 9-5 Offset: 4-0 I ...
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Getting the flit size in a Tiled Chip Multicore Processor(TCMP) system with a mesh architecture

Consider a TCMP system with, say, a 4x4 mesh Network on Chip (NoC) where each tile has a superscalar processor. It is given that that the TCMP uses 64-bit words and the inter-router link bandwidth is ...
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Tag storage when using HBM as an L4 cache

I'm reading through Computer Architecture: A Quantitative Approach, Sixth Edition, and I'm trying to understand the issues surrounding tag storage in using HBM as an L4 cache. The primary concern ...
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Confusion about “false sharing”

This is a homework problem that I have In a multicore system, you are running the code on the right on each core, and it suffers from false sharing. You can assume ...
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Where should I start to understand how computers work? [duplicate]

I am interested in how computers work but I have no idea how the concept of 0's and 1's converts to making possible for people to control a computer by programming. I would like to understand from ...
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MIPS pipeline: choosing between slowing down a stage and adding a new stage

Suppose a new, more complicated, instruction is desired for this simple pipelined MIPS processor. Suppose, also, it could be implemented by either (a) adding new logic to the execute stage of the ...
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Help with performance and speed-up question related to number of cores and their areas

There is a question in my exam that said: Consider the following three processors (x, y, and z) that are all of varying areas. Assume that the single-thread performance of a core increases with the ...
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Computing average access time

A computer has a cache memory and a main memory with the following features: - Memory cache access time: 4 ns - Main memory access time: 80 ns - The time ...
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Procedure for finding if Overflow occurs on addition

I have two 4-bit 2's complement numbers a,b, and their sum in s (Also a 4-bit 2's complement number). Using only the basic logical operations, I need to write a procedure to find if an overflow occurs....
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Binary to ASCII using logical operations

I am learning Computer Architecture from Introduction to Computing Systems (2nd Edition) and am stuck on this question. What operations can be used to convert the binary representation of 3 into ...
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Finding the timestamps of processes implementing Lamport's clocks

I have been asked this question, but don't know how to go about answering it. Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
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How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
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Floating point binary number to a 7 segment decimal display

I have covered floating point (32 bit) conversion from float to decimal and decimal to float. I am happy with the theory and I have created a conversion tool in Excel VBA which works just fine ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the architecture most likely to have?

Working through some material on CPU architecture and am unsure on the following question: Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the ...

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