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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Is there a service provided by the OS, which is NOT accessible by the terminal emulator?

Is there a service provided by the OS, which is NOT accessible by the terminal emulator? If so, how else would the user be accessing it? (My guess is, there wouldn't be since that would be silly. But ...
Lucky's user avatar
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Is it possible to completely remove a pre-installed OS from a manufactured computer?

I was told by my professor that when a computer is manufactured, it comes with an OS where the OS is installed in two different parts. The first part is physically "hardwired" (?) into the ...
Lucky's user avatar
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Basic questions regarding a computer

I'm an Undergraduate CS student. My understanding of a "computer" is that it is simply a machine that can "carry out" a set of instructions. The set of instructions it can ever ...
user1514263's user avatar
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Floating Point to Integer Conversion (fcvt.*) hardware implementation

In the RISC-V specification, there is support for the conversion between floating point and integer numbers, in particular the fcvt* class of instructions. I'm wondering what the hardware ...
Andrew Miller's user avatar
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Why is ROM read only? And why do SSDs use it?

I was researching about SSDs and ended up going further and reading about how it uses flash technology which from what I gather is pretty much an EEPROM, which (I might be wrong on this) is just an ...
WaveCave's user avatar
1 vote
2 answers
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Why is the default page/block size 4 KiB?

Clearly, some empirical study on an older machine helped us choose a 4KiB page size to balance TLB hit rate and fragmentation. Modern hardware and operating systems support this size for backward ...
idle_cycles's user avatar
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Is there a delay between two commands to read data from RAM?

Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
Slaycapь's user avatar
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Byte addressing and alignment

With byte addressing, the CPU can access a single byte. But how does this access happen during alignment? As I understand it, if a CPU needs to read an unaligned byte, it reads the word starting from ...
Slaycapь's user avatar
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MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?

I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following ...
Juan De Castro's user avatar
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Daughter-board multiplier

I am writing a program in TI Code Composer Studio assembly-only empty project using the MSP-EXP430FR6989. The assembly-only empty project uses MSP430 Assembler Code Template for use with TI Code ...
Logan Andrew LiVigni's user avatar
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Are modern ram architectures (DDR4 or SDRAM) Multi-port or Dual-port?

So I recently learned about dual-port and multi-port RAM but I tried doing some research on modern RAM architectures and if they use it but I couldn't find anything on it.
Cookie Infinity's user avatar
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Why do two pairs of identical DDR4 RAM not work together?

Several years ago, I tried to get two identical pairs of DDR4 RAM to run together in my computer. I have since bought a set of four, but I've always wondered why the RAM didn't work. Its been long ...
Sam Chamberlain's user avatar
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Measuring Cache Access Time

I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them: ...
Agustín Núñez's user avatar
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1 answer
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How CPU uses wider address bus than register size?

i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). ...
piotrek's user avatar
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Expected hit ratio for a cache

I am trying to understand how to approach the question below which is a coursework question. I understand that each memory request is 32 bits and so there will be 262144 requests. There are 42 blocks ...
Euridice's user avatar
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Issue understanding how control signals are pipelined in a RISC architecture

I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding: ...
Micronuno's user avatar
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The Atlas system word addresses

I'm reading about the Atlas operating system and I came across this: The Atlas system used a British computer with 48-bit words. Addresses were 24 bits but were encoded in decimal, which allowed 1 ...
beginwithc's user avatar
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What is Representation Invariant?

I was the book "Introduction to Computation and Programming Using Python" and I stumbled upon the concept of representation invariant. What I understood is that the variables (and maybe ...
Godoy's user avatar
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Memory addresses requested by CPU vs Memory Address Provided to DRAM

So, i just got through studying DRAM architecture. I learned that a row address, column address, bank number etc are provided to the DRAM during a read operation. Based on the address provided, 64 ...
Alice's user avatar
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Relation between MTTF (Mean Time to Failure) and FIT (Failure in time) in computer architecture

I have a doubt regarding relation between MTTF (Mean Time to Failure) and FIT (Failure in time). Is it FIT = 1/(MTTF1 + MTTF2 + ...) or FIT = 1/MTTF1 + 1/MTTF2 + ... ?
Vamsi Krishna's user avatar
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relationship between page table size, patge table entry and pagt table base register alignment

I am trying to understand this question from Prof. Onur Mutlu's assignment solution on virtual memory. I am reproducing the problem and solution followed by my question: Problem: A dedicated computer ...
Singh's user avatar
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Best solution architecture for: Intelligent chat to retrieve information from specific sources

I am trying to design best solution for a chat application based on LLM model which has set of functions and based on user input can retrieve the information. I would like to ask you for some ...
Rafał Sokalski's user avatar
2 votes
1 answer
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Problem with cache and memory from university class

In my university class, I received this homework assignment on computer architecture, but I don't know how to solve it. I already know that the correct answer is 0, but I don't understand why. Could ...
H0t_blue_B0i's user avatar
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How many operands does the NOP instruction have?

At first I thought it is obvious, since the NOP instruction does not have any operand, we say it is zero-operand instruction. But then looking on the zero-operand ...
tbhaxor's user avatar
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Load Store Hazard

I recently had an interview to identify all of the hazards in the following instruction set. I was told by the interviewer that there was some hazard between instructions i3 and i4 and it's not a RAW ...
johnbon's user avatar
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When a CPU copies instructions from storage into RAM how does it jump to instructions no longer in RAM?

When a CPU needs to get more instructions from storage and copies them to RAM, how does the CPU jump to previous instructions that are no longer in the RAM? Would it have to copy the old instructions ...
Thenboy's user avatar
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8086 number of memory segments in the user's accessible memory

I had an exam question which says how many segments the user accessible part of the 8086 memory contains? I have count it using this: Since from $00000$ to $0007F$ and $FFFE0$ to $FFFFF$ are made for ...
Alan Ari's user avatar
2 votes
1 answer
70 views

Calculate the CPI of a program

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First_1st's user avatar
1 vote
1 answer
51 views

Has there been a processor architecture that included commands that move arrays of data in the memory with one opcode?

In traditional processors one move operation can at most move one word between memory locations and optionally increment or decrement the registers which point to those memory locations. In x86 ...
Anixx's user avatar
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Why can't I use data forwarding in this exercise?

as the title says, I am wondering why this exercise doesn't show a data forwarding from the "ex" stage of 2nd instruction to "ex" stage of 3rd instruction. P.S. the architecture is ...
unrealyozora's user avatar
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How do you tell whether a binary number is positive or negative?

Consider the figure in Exercise 2. If the current machine code that executes is 0x214bfffd and the values of the registers in the processor are as shown below, what is then the value of the input WD3 ?...
First_1st's user avatar
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Why does Elbrus use VLIW architecture?

I find the Russian Elbrus CPU fascinating. It seems that it is fairly decent at performing calculations, and security. This is likely as it is heavily specific for military and financial industries, ...
securityauditor's user avatar
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How does signed floating point adder implement?

The following picture is a block diagram of an arithmetic unit dedicated to IEEE 754 floating-point addition from Computer Organization and Design RISC-V Edition: The Hardware Software Interface 2nd ...
user153245's user avatar
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Why when calculating how long it would take to read a file from a harddrive do I not use transfer speed per sector?

I'm working on a problem from my textbook (not homework, just an example), and it asks us to calculate the 'best case' scenario of reading a 1MB file from the hard drive. I don't know why the right ...
PerformingAlbatross's user avatar
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Expressing Boolean Functions In Terms of Another Function

Given two boolean functions f1 and f2, are there any tools available that could be used to automate the process to represent f1 in terms of f2? I understand the process of this doing this by hand ...
rotatinglemur's user avatar
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1 answer
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clock chip (not the CPU clock) replacement on my BEMER medical device

the 24 hour clock/timer on my BEMER PEMF device's microprocessor is keeping erratic time lately. Shortly after I reset to the correct time, it fails to keep accurate time. I'm wondering if exposing ...
Loperman's user avatar
1 vote
0 answers
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How can I connect a drive to a 16 bit custom intel 8088 system?

I'm embarking on a long-term project, aiming to build a computer based on the Intel 8088 architecture. This venture provides an excellent opportunity to deepen my understanding of computer hardware ...
Grizzly's user avatar
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What are some good books for vlsi cmos design? Or some good educational software?

I'm a student trying to learn more about CMOS design, I already understand assembly and computer architecture, but VLSI is very interesting and I was wondering if you guys knew some good books/games ...
1grungler1swag's user avatar
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Understanding atomic requests/transactions in a snooping coherence protocol

I've been reading the book "A Primer on Memory Consistency and Cache Coherency", and it contains the following paragraph: The Atomic Requests property states that a coherence request is ...
eof's user avatar
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1 answer
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Regarding CPU ILP: what actually consistitutes "the current instruction"?

If a CPU is able to execute multiple instructions in parallel, and fetching/decoding/scheduling instructions happen in batches, and there's multiple execution units, etc. What does the IP register ...
ABu's user avatar
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How do you understand Systolic Arrays?

I'm working on a problem from the Digital Design and Computer Architecture course on Systolic arrays. The question set up is as follows: The following diagram is a systolic array that performs the ...
Connor's user avatar
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Is the optical disk drive an input device?

I have read online and seen websites saying the optical disk drive is a storage device. In my opinion, the optical disk drive only writes data to the optical disk so it's not a storage device, am I ...
Lucretius's user avatar
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1 answer
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How are pointers modeled on bit-based computer models?

Why bit-based computer models? The perhaps most commonly used computer model is a random access machine that can store natural (or even real) numbers in infinitely many cells indexed by natural ...
KGM's user avatar
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1 answer
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Counting the expected number of CPU cycles for n-number of assembly instructions

I was trying to count the cpu_cycles from an ARM processor 4 core Cortex A78 to be exact) using the PMU registers. Now, at the beginning, I read the cpu cycles counter register, then for test just run ...
Adeesh Lemonickous's user avatar
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Amdahl's law to determine the overall speed increase using the optimizations

There is an old CPU running a program in which memory operations currently take 30% of its execution time. Scientists find that adding a cache memory speeds up 80% of memory operations by a factor of ...
tanisha's user avatar
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1 answer
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What is the relation of branch instruction in single core CPU v.s. multicore CPU?

In the Computer organization and design book, there is an exercise in chapter 1 that stated: ...
user153245's user avatar
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3 answers
141 views

Logical address vs physical address

I have been trying to understand the logical and physical address of some data/instruction the logical address is a address generated by the CPU during a execution cycle.So if I write this code ...
Cerise's user avatar
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Neural networks as building blocks of a computer

I think I have developed a logic circuit which by using combinational logic and flip flops learns to perform the XNOR logic between 2 bits.It is a kind of state machine. Suppose we built a computer ...
Cerise's user avatar
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Understanding the Relationship Between CPU Registers Amounts and Maximum RAM in 32-bit Architectures

To my knowledge, The number of CPU registers can tell us the maximum RAM we can have. I am only talking about physical memory, no virtual memory or virtualization in my question. A 32-bit CPU ...
Ahmad Addas's user avatar
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1 answer
201 views

Sequence counter in a hardwired control unit

I have been studying the structure of a hardwired control unit and at 8:57 of this video we get a basic block diagram.What does the sequence counter do exactly?
Cerise's user avatar
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