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Questions about the organization and design of computer hardware.

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0answers
22 views

My computer is not turning on [on hold]

After switching it on, I have to wait for 20-50 minutes sometime 1-1:30 hrs to turn it on till then the display is showing this message "No HDMI Cable". If anyone can help me then please do.
1
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0answers
6 views

Why is the method of im2col with GEMM is more efficient than the method of direction implementation with SIMD in CNN

The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement convolutional layers is to expand the image into a ...
0
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0answers
6 views

How program counters with feature “Read from bus Enable”, “Write to bus Enable” and “Count Enable” is designed?

I have been designing program counter that has a features like "Read from bus Enable", "Write to bus Enable" and "Count Enable". I have already designed binary counter And Read from bus Enable using ...
1
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0answers
26 views

how many boolean functions exist that satisfy the condition

how many boolean functions exist that satisfy the condition : $Not[f(x_1,x_2,x_3,....,x_n)]$ = $f(Not(x_1), Not(x_2),...,Not(x_n))$
0
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0answers
13 views

Is there an architectural difference between consumer grade mobile processors and their desktop counterparts? [closed]

I'm specifically interested in the Intel Core product line. For example would a Core i5 8th gen desktop processor just be clocked higher with additional cores as compared to a Core i5 8th gen mobile ...
0
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0answers
12 views

Software Design Diagrams [closed]

I want to design diagrams for the Applications I developed. I have only being designing Architecture Diagrams using Microsoft Publisher, which Limits me. Can anyone advise the best site to learn ...
0
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2answers
50 views

How can a 64-bit processor address 2^64 different memory locations at a time?

I understand that a 64-bit processor can hold a 64-bit long address and that a 64-bit address can represent $2^{64}$ different values. But I don't understand why that processor can address $2^{64}$ ...
0
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0answers
21 views

Calculate the throughput of the network for the given number of terminals in ALOHA [closed]

I am trying to solve this problem. I would appreciate if someone can check if my approach is correct. Part 1 Consider a network based on pure ALOHA with Poisson distributed traffic. If the success ...
0
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0answers
4 views

What is the overall average access time of a memory hierarchy with write through policy?

Given that we have 3 levels of memory. the time it takes to transfer a word from level i to i+1 being 4Ti where Ti is the time required to access memory level i Mi is the miss ratio of memory level ...
0
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1answer
28 views

Making sure the Branch Target Buffer stays accurate

As i've been told , a Branch Target Buffer (BTB) acts a lot like a cache for Branches , keeping a map of where branches are in the address space. If implemented well , it should allow the processor ...
1
vote
1answer
36 views

Why are FPGA's less efficient than fully hard-coded ASIC's?

A Field-programmable gate array (FPGA) is generally more efficient than using a "hard-coded" processor like a CPU or GPU for highly specific applications like bitcoin mining or doing structurally ...
1
vote
1answer
23 views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
0
votes
1answer
30 views

General question on choosing an Assembly language based on my goal

So I know assembly is so big and it seems learning assembly is like learning high level programming, you don't need to learn them all, you can learn couple and this will be enough. The thing is with ...
1
vote
2answers
35 views

How are CPU architecture and word size related?

I did lot of research on internet but couldn't get my answer. I want to know what is the difference between the word size and CPU architecture? For eg.- I read that CPU of 32-bit architecture can ...
3
votes
2answers
52 views

Does Assembly Language depend on an Assembler or the family of processor?

From what I understand, the x86 family of processors understands the same instruction set and x86-32, x86-16 machine code can be executed by an x-86-64 processor because of backwards compatibility. ...
1
vote
1answer
22 views

Are space allocated to C/C++ variables in secondary storage also in Compiled file?

Are data segments,heap,stack etc also present in secondary memory with compiled code then later mapped by OS to RAM when I open it?
0
votes
1answer
30 views

Does using micro-operations require a higher clock rate than listed

Say we have a modern (Skylake, say) Intel CPU running at a fixed 5GHz clock rate. Since Intel CPUs run micro-operations internally and reaches > 1 instructions per cycle, it needs to be able to run ...
1
vote
1answer
63 views

accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
1
vote
1answer
30 views

difference between minus and subtract microoperation

While reading Computer Architechture book by M.Mano. I came across Arithmetics Microoperations sections which has two microoperations which confuses me a lot, R3 <- R1 - R2 ( Minus ...
0
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0answers
25 views

The number of cycles needed to execute the following loop in pipeline processor?

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute ...
0
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0answers
19 views

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
1
vote
1answer
48 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
1
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2answers
47 views

Can a processor without stack pointer registers, have a subroutine calls and interrupts?

Suppose a processor does not have any stack pointer registers, which of the following statements is true? It cannot have subroutine call instruction It cannot have nested subroutines call ...
0
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1answer
39 views

Pipeline question

I have this multiple choice question from a computer architecture class, a mips processor executes a program at 10 sec, without pipelining and clock rate 100 MHz. When running the program on a ...
4
votes
1answer
69 views

Are multiple interrupts generated when I hold down a key on my keyboard?

When I hold down a key on my keyboard, a continuous stream of characters is generated and is displayed on the text editor, Now since pressing a key is a hardware interrupt, so does holding down a key ...
0
votes
1answer
40 views

Processor pipelining question: number of instructions per second

A question from the textbook Modern Operating Systems by A. S. Tanenbaum reads as follows: A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, 1 nsec. ...
0
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0answers
11 views

Difference between throughput, latency and cycle time in monocycle/multicycle?

Referring to this question, I did not quite understand how these concepts apply when talking about monocycle and multicycle architectures.
0
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0answers
23 views

How does DDR3 & DDR4 memory interact with the cache? What are the differences?

I looked up how these two protocols work, but I could not find any legitimate sources. Please provide any if you know. Thanks!
4
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0answers
41 views

Is every von neumann machine turing complete?

I understand that TM is a 'Model of Computation' which tells us about the computational power of a machine while Von Neumann Architecture is a 'System Architecture' that tells us about how the machine ...
1
vote
0answers
39 views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
0
votes
1answer
51 views

SIMD Utilization

Can anyone help me understanding this exercise? We define the SIMD utilization of a program run on a GPU as the fraction of SIMD lanes that are kept busy with active threads during the run of a ...
-3
votes
1answer
25 views

Calculate the storage capacity of this disk in GB [closed]

A disk pack has 12 platters ( plates) having 2048 tracks on every surface. It can store 1024 bytes per sector ( assume each track has 512 sectors). Calculate the storage capacity of this disk in GB.
1
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1answer
47 views

Difficulty understanding the faster multiplication hardware

This is a picture of faster multiplication hardware taken from Computer Organization and Design (5th Edition). I'm having some difficulty understanding it. I was trying to simulate this for a test ...
0
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0answers
15 views

How much is VLIW power- and area-efficient then superscalar anyway?

Most of texts say VLIW, which is lack of hardware to detect hazards and schedule the instructions. But I haven't see any evaluation about how much VLIW can save area(h/w complexity) and power compared ...
0
votes
1answer
28 views

Valid bit incoherence between TLB and Page Table

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
0
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3answers
73 views

Is it 100% OK to say “All software doesn't need to know the system lower than the architecture level”?

Most of you know this diagram. If this diagram is true, all software is free to not know the levels lower than ISA. But it's not true. Softwares like performance-critical programs or system softwares ...
0
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0answers
40 views

Cache mapping problem

Okay.I have problem about cache mapping. Here is the problem . Memory size is 1 MB Byte addresable Cache block size is 16 Bytes. Cache size is 64kb Since memory is 1 mb=2**20 Bytes. So we need ...
1
vote
1answer
38 views

Calculating the probability of data loss of a RAID 1+0 system

I have a task where a RAID 1+0 system (A RAID 0 connects two RAID 1's with two disks each = makes 4 disks in total) is given with no further details. Then let p be the probability that one disk shows ...
0
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2answers
34 views

How does RAMDAC get notified about framebuffer write?

I'm learning computer graphics, and I read this course lecture in order to understand how graphics I/O works under the hood. But the following explanation was not very clear to me: The values in ...
1
vote
0answers
100 views

Cache Hit or miss

Asume 512 Bytes direct-mapped cache with 64 Byte cache blocks (cache line size), is empty at the beginning and below given set of physical addresses are referred by CPU in the given order. At each ...
0
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1answer
20 views

How will the value, A(2) be available in, line 2, if A(2) is being calculated in, line 3?

How will the value, A(2) be available in, line 2, if A(2) is being calculated in, line 3?
1
vote
1answer
42 views

Program Counter Incrementation When instruction Is More Than One Word

How is program counter(PC) incremented when instruction takes more than one word? How does PC know when to increment by one word or by more than one word since incrementation is done before decoding ...
0
votes
1answer
49 views

NX Bit in x86 vs x86_64

I've been reading about how the kernel manages memory in x86 from this popular blog post(https://manybutfinite.com/post/how-the-kernel-manages-your-memory/) and had a few questions. There is a part ...
0
votes
1answer
32 views

Virutalization of peripheral device

I have this question to answer: "Please shortly explain how an interface virtualizes a peripheral device to the CPU." I don't really understand what the question is asking for. I know the theory ...
0
votes
1answer
29 views

What the heck is a memory channel “CS bus”?

While I was reading about memory architecture from the CMSC 22200's Lecture 17 of University of Chicago, I got stuck on determining the meaning of the word "CS" used for describing a bus as part of ...
2
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1answer
52 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
-3
votes
1answer
55 views

How many bits does a data bus need to have? [closed]

Using the following context as an example for the calculations: Data bus connecting the processor to a memory 32 bits, considering a memory with capacity of 16kB. How many bits does a data bus ...
1
vote
1answer
136 views

How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw $a0,...
17
votes
5answers
4k views

What does machine code actually look like while being run?

When machine code is actually being executed by hardware and the CPU, what does it look like? Would it look like binary, as in instructions being represented by ones and zeros, or would it be ...
1
vote
1answer
24 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...