Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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questions
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In a single cycle datapath, do 'decode' and 'operand fetch' occur simultaneously?
After instruction has been fetched, does it go to control unit and register file at the same time or one after the other?
For example if the control unit and register read both have 80ps delay, and we'...
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11 views
Cache Blocks Direct Mapping
If the main memory address has 18 bits (7 for tag,7 for line and 4 for word)
and each word is 8 bits.
I found that the main memory capacity is 256-KBytes, total cache lines is 128 line,
total cache ...
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0answers
10 views
Is there a tool or simulator for 5 stage mips pipeline that detects data and control hazards?
Title says it all. Tried different tools but was not successful.
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0answers
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Detecting Data and Control Hazards for a mips 5 stage pipeline
I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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2answers
28 views
Big-endian systems and the smallest memory address
I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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1answer
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Functions of CPU
What part of the CPU communicates with all the other parts of the processor and makes the processor faster by containing frequently used data or instructions?
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direct-mapped cache
problem is as follow:
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits)
Tag: 63-10
Index: 9-5
Offset: 4-0
I ...
1
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0answers
7 views
Getting the flit size in a Tiled Chip Multicore Processor(TCMP) system with a mesh architecture
Consider a TCMP system with, say, a 4x4 mesh Network on Chip (NoC) where each tile has a superscalar processor. It is given that that the TCMP uses 64-bit words and the inter-router link bandwidth is ...
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1answer
23 views
Tag storage when using HBM as an L4 cache
I'm reading through Computer Architecture: A Quantitative Approach, Sixth Edition, and I'm trying to understand the issues surrounding tag storage in using HBM as an L4 cache. The primary concern ...
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Problem solving an exercices in system architecture
So hey guys hope you are doing well. I have aproblem solving this exercices. I have tried a lot but it seems my answer are always wrong
first here is the problem:
In the case where these registers ...
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2answers
39 views
Confusion about “false sharing”
This is a homework problem that I have
In a multicore system, you are running the code on the right on each core, and it suffers from false sharing. You can assume ...
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0answers
25 views
Computer Architecture Problem
A computer system has a 64KB main memory and 1 KB space for the cache memory, and transfer between cache and main memory is 16 * 8 Blocks,
uses 2 space blocks in each set(uses set associative), and ...
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3answers
794 views
Where should I start to understand how computers work? [duplicate]
I am interested in how computers work but I have no idea how the concept of 0's and 1's converts to making possible for people to control a computer by programming. I would like to understand from ...
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1answer
22 views
MIPS pipeline: choosing between slowing down a stage and adding a new stage
Suppose a new, more complicated, instruction is desired for this
simple pipelined MIPS processor. Suppose, also, it could be
implemented by either (a) adding new logic to the execute stage of the
...
0
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1answer
22 views
Help with performance and speed-up question related to number of cores and their areas
There is a question in my exam that said:
Consider the following three processors (x, y, and z) that are all of varying areas. Assume that the single-thread performance of a core increases with the ...
0
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1answer
29 views
Computing average access time
A computer has a cache memory and a main memory with the following features:
- Memory cache access time: 4 ns
- Main memory access time: 80 ns
- The time ...
0
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1answer
27 views
Procedure for finding if Overflow occurs on addition
I have two 4-bit 2's complement numbers a,b, and their sum in s (Also a 4-bit 2's complement number). Using only the basic logical operations, I need to write a procedure to find if an overflow occurs....
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1answer
38 views
Binary to ASCII using logical operations
I am learning Computer Architecture from Introduction to Computing Systems (2nd Edition) and am stuck on this question.
What operations can be used to convert the binary representation of 3 into ...
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0answers
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Finding the timestamps of processes implementing Lamport's clocks
I have been asked this question, but don't know how to go about answering it.
Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
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2answers
24 views
How does a cache handle overwriting between 2 addresses in the same block?
Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block.
First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
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0answers
23 views
Floating point binary number to a 7 segment decimal display
I have covered floating point (32 bit) conversion from float to decimal and decimal to float. I am happy with the theory and I have created a conversion tool in Excel VBA which works just fine ...
0
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0answers
17 views
Size of the data bus connecting CPU cache and RAM?
I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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0answers
9 views
Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the architecture most likely to have?
Working through some material on CPU architecture and am unsure on the following question:
Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the ...
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1answer
73 views
What purpose was the Von Neumann machine intended for? And what hardware limitations existed when von Neumann invented it?
Its namesake invented the Von Neumann architecture (VNA) in a specific computing environment and a specific context. In light of those two:
What kind of limitations was the VNA designed to work with?
...
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0answers
14 views
why we need pipeline registers in pipeline processor ( as for example for MIPS processor )
I think the answer because the data of an instruction can be overridden by the data of the instruction that will be fetched after it , but I think the data of the first instruction will always be ...
0
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1answer
20 views
Single Cycle Data-path Requirements
How does having separate instruction and data memories help in implementing a single cycle datapath for a MIPS instruction set? I want to know why we can only use a datapath element once in a cycle ...
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1answer
79 views
Would it be possible for a new technology to make RAM obsolete?
If a new technology is invented for storage devices, which is the same as or speeder than RAM (bandwidth&lanecy), is it possible to make RAM obsolete and consider the storage device as the main ...
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3answers
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Why is the Nintendo Entertainment System (NES) referred to as an 8-bit system, rather than a 1-byte system?
As far as I've understood it, referring to this system as an 8-bit system points out that one can access 8 bits of data in one instruction.
While I understand that we're not saving vast amounts of ...
2
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2answers
64 views
How is Memory Segmentation done in 8086?
Basically what I know is that 8086 can address up to 1 MB of locations which are divided in 4 segments(code, data, extra and stack) 64 KB each. But 64 KB * 4 is 256 KB, which doesn't add up to 1 MB(...
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0answers
22 views
How to predict the time complexity of matrix multiplication and inverse on a GPU?
Nvidia GPU can speed up the matrix manipulation greatly. I want to have a basic idea to predict the consumed time for matrix manipulation.
How can I analyze the time complexity of matrix ...
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11answers
5k views
Why do logic gates behave the way they do?
I am a Software Developer but I came from a non-CS background so maybe it is a wrong question to ask, but I do not get why logic gates/boolean logic behave the way they do.
Why for example:
...
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1answer
32 views
Representation of -40 in 8bit computer using 2's complement
What is the representation of -40 in a 8bit computer using 2's complement intiger?
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35 views
why does Register write(RW) stage of a single cycle processor takes the shortest time to execute? Explain your answer
I can't seem to find the explanation for why RW stage of a single cycle processor takes the shortest time to execute. Can anybody explain why this is so.
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Confused about computer architecture classification
Computer architecture are generally classified with respect to ISA. I want to know the relation between ISA to flynn's taxonomy vs harvard/von-nuemann architecture. Partial confusion is that most of ...
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2answers
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What needs led to the implementation of ASCII codes?
Prior to ASCII existing, we already had at least four number systems, namely
Binary
Decimal
Octal
Hexadecimal
So what were the needs that lead to the ...
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0answers
24 views
If there is a cache miss can we consider extra memory accesses because it has to fetch data from the main memory?
A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store ...
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0answers
7 views
Determining which block a word will be mapped to
Is it possible to know which block in a cache a word will be mapped to if you do not know how many bits each word has? I have this problem that seems incomplete to me.
The question asks something ...
0
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1answer
57 views
Why is the opcode 0 for all r-type instructions? Please explain your answer
I can't seem to find the explanation for why all r-type instructions have opcode 0 always. Can anybody explain why this is so.
0
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2answers
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Are interrupts only found in BIOS?
I may be misunderstanding here-- but are interrupts only found in BIOS and not UEFI systems?
More context:
"Through standardized calls to the BIOS (“interrupts” in computer parlance), the operating ...
0
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1answer
26 views
Memory Addressing - Alignment Clarification
I'm reading "Computer Architecture A Quantitative Approach" (5th edition) and I'm having a hard time understing this table:
I understand how Misalignment happens, i.e., some byte, half-word, word, or ...
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3answers
98 views
The maximum decimal integer that can be stored in memory of 8-bit word processor computer?
Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e
The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ?
a)...
2
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1answer
43 views
Really confused about latency with pipelining
I finished watching a video about pipelining https://www.youtube.com/watch?v=eVRdfl4zxfI
which I thought made sense.
Latency is the amount of time it takes to complete each instruction. Even with ...
2
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0answers
39 views
What is “orthogonality” in the context of Instruction Encoding?
What does it mean by "orthogonality" in the context of Instruction Encoding?
Why CISC Architecture is orthogonal while RISC is not?
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0answers
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How fast can 10 integer multiplications be executed?
This is self study, but not homework. I am reviewing some slides I found online and have come across the following question.
Question:
If the latency of integer multiply is $3$ and the cycles/issue ...
2
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1answer
110 views
Why the Call instruction in the x86 architecture saves the return address as EIP+5 instead of 4?
In 'The Computer Organization and design book' it illustrates the call instruction as
Decrementing the stack pointer by 4.
saving the EIP+5 into the stack.
Jumps to the new address specified.
What ...
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2answers
297 views
how pseudo direct addressing works?
In pseudo direct addressing mode (For the MIPS architecture) the 26 bit of the jump instruction are joined to the upper 4 bits of the PC .
how could this help in jumping to relative positions suppose ...
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1answer
57 views
What does it mean to isolate a field in a word?
I have been reading in the 'computer organization and design' book and I encountered this section:
what operations isolate a field in a word
I know that the ...
2
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1answer
56 views
Bus and System Clocks
What is the difference between a Bus clock and a System Clock? Do they function the same way? I have been reading about System clocks but I can't really find anything about bus clocks in my book to ...
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Amdahl's Law and efficient algorithms
Does the efficiency of algorithm leading to better performance of the system can be attributed to Amdahl's Law?
or
Is the Amdahl's law only applicable for the analysis of efficient hardwares and ...
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1answer
51 views
How does the hardware of a while loop work?
I know get how logical operators for if logic gates work, but I am trying to understand how while loops fit into that picture. I realize that this question is a bit vague. It all started because I was ...
