Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

0
votes
0answers
25 views

Why does Skillicorn's Taxonomy allow us to design 30 models?

In Skillcorn, David B, "A Taxonomy for Computer Architectures", IEEE Computer, 21(11):46-57, Nov 1988, a taxonomy of multiprocessor architectures is described. My teacher said that Skillikorn's ...
0
votes
0answers
14 views

How do I find the sampling rate? And what is the formula for sampling rate? [on hold]

Suppose you have a 100 MHz CPU and a A/D converter with an 8 kHz sampling rate. Samples of the A/D converter are 32-bits. What is the sampling rate? and how do I get the formula for the sampling rate?...
1
vote
2answers
39 views

What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
0
votes
3answers
40 views

Does increasing k in a k-way set-associative cache always lead to a better miss rate?

As far as I know a 2-way set-associative cache works better than a one-way one considerably but going to 4 and 8-way caches leads to a marginal improvement. My question is: does increasing K (going ...
-2
votes
0answers
14 views

Where are the Condition flags stored in Y86-64 ISA? [closed]

The Condition Flags SF, ZF and OF, in the fictitious Y86-64 architecture, as described in Computer Systems, a Programmer's Perspective by Randall and Bryant.
0
votes
0answers
34 views

CRC computation speed vs polynomials features

I tried to find information about how features of a CRC polynomials influence computation speed of implementations. It is obvious that (depending from the CPU architecture the algorithm runs on) ...
0
votes
0answers
34 views

How does computer work? [duplicate]

I am not a computer scientist or even a student of CS. I just want to find more information and would like if someone could put if in right direction about how actually computer works. I understand ...
0
votes
1answer
24 views

The instructions a Stack Machine has

Trying to figure out which instructions a stack machine has, and wanted to clarify / reassure that these are in fact all of them. push onto stack ...
-1
votes
0answers
6 views

When does the BIOS Bootstratrap need which components, when does it fail? [migrated]

When I power on my PC it first waits for the Power Good signal, if I understand correctly this works without the CPU and RAM. Then it loads from the ROM into the RAM and executes the BIOS. If either ...
4
votes
0answers
34 views

What's the difference between the XOR instructions “VPXORD”, “VXORPS” and “VXORPD” in Intel's AVX2 [migrated]

I see in AVX2 instruction set, Intel distinguishes the XOR operations of integer, double and float with different instructions. For Integer there's "VPXORD", and for double "VXORPD", for float "VXORPS"...
1
vote
2answers
54 views

If a NAND gate is universal, why you don't have NAND OISCs

If a NAND gate can be used to construct all other of the basic logic gates, then I'm wondering why you don't/can't have a purely NAND-based One Instruction Set Computer (OISC). All the OISC single ...
1
vote
0answers
18 views

Minimum no. of flip flops for the given sequence

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of flip-flops required to implement this counter is________ According to me, the ...
2
votes
1answer
35 views

Examples of logic gates using non-standard models

These are the only ones I have been able to find online: Pulley Logic Gates Marble adding machine MARBLE COMPUTER LOGICAL AND GATE I would like to find some more discrete models like these (as ...
0
votes
1answer
11 views

Maximum number of nodes connected when the link has a large buffer

A link of capacity 100 Mbps is carrying traffic from a number of sources. Each source generates an on-off traffic stream;when the source is on, the rate of traffic is 10 Mbps, and when the source is ...
3
votes
2answers
63 views

What is the avantage of having memory mapped I/O?

I can't make out what is the avantage of it comparing with the port designed I/O Is it faster? Is it more reliable? Is it cheaper?
0
votes
1answer
23 views

From where does the Fetch Unit get its instructions?

In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
0
votes
0answers
28 views

Do I need a implicit digit in a base-10 machine?

If I have a base-10 machine, Do I need a implicit bit or all numbers for mantissa take all bits? When I say bits, I mean digits. Since in a base-2 machine, You have a implicit bit. My question is if ...
2
votes
1answer
28 views

In which category is the supercomputer SUMMIT according to Flynn's taxonomy?

I have read that the POWER9 processor is an SIMD processor. I have also read that most supercomputers are MIMD based. So is the SUMMIT supercomputer SIMD? And if it is can you name a supercomputer ...
1
vote
0answers
32 views

From nand to numbers [duplicate]

My understanding is that computers are basically made of nand gates, and that all other gates, such as and, or, etc, can be made from nand gates. So far so good, but how do we get from nand gates to ...
-2
votes
0answers
31 views

What are expanding opcodes? What are they good for? What would be a simple example?

I really am in need of some thorough explanation here. A little bit simpler and more understandable than in the textbooks or youtube slides lectures. Turned out to be slightly more complicated to ...
0
votes
1answer
30 views

Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
9
votes
0answers
139 views

How would a CPU designed purely for functional programming be different?

CPU's are to an extent designed with in mind the software that people will write for it, implicitly or explicitly. It seems to me that if you look at the design of instruction set architectures, ...
1
vote
1answer
38 views

If there is any sense of an optimal set of instructions in an ISA

So there are One Instruction Set Computers, having only one (complicated) instruction like addleq, "add and branch if less than or equal to zero". And then there ...
2
votes
3answers
93 views

How does a computer “wait” time?

Me and a friend were discussing how programming languages can perform asynchronous tasks, like waiting 15 seconds before performing another task, and we started a debate. I know that computers have ...
-2
votes
1answer
48 views

How to find the definition of Computer Architecture terms in Compter Science? [closed]

To find the meaning of computer architecture terms in Computer Science do I need to use a Computer Science book? Do I need to find the computer architecture terms in a Computer Science Dictionary or ...
1
vote
2answers
49 views

If you can represent/model a Conditional IF statement with AND + NOT or OR + NOT

I am still trying to wrap my head around this, which shows how to simulate control-flow without using an if-statement. I've been looking at basic logic today and ...
0
votes
1answer
31 views

If the MOVE instruction in a Transport Triggered Architecture can implement a NAND gate (as a Functional Unit)

Background I'm looking at Transport Triggered Architectures (also this), linked to from an OISC page listing many different 1-Instruction Set Computers. It basically says the following: TTA ...
0
votes
0answers
25 views

If only using bit-shifts can produce a Turing-machine, or if you need more bitwise operations

So you can have One Instruction Set Computers. But typically these instructions have rather complicated underlying implementations. addition (addleq, add and branch if less than or equal to zero) ...
0
votes
2answers
52 views

How “add” could be implemented in only bitshift operations

Typically, add/subtract/multiply/divide are primitive operations in an Instruction Set Architecture (ISA). I am interested to know if they can instead be implemented efficiently using only bitshift ...
1
vote
0answers
12 views

Is there one or more Page Tables

I saw a question similar to this one, and it was answered but the answer was kind of vague and I'm looking for a little more detail than that. The question I'm referring to is this one. The answer ...
1
vote
1answer
49 views

How are words assigned in machine language?

So, if you have an 8-bit computer and it can perform a fetch cycle, meaning it can access its memory, how do you create words the computer understands. If LDA "load the accumulator" is in the ...
3
votes
1answer
20 views

When to free physical registers

When we do register renaming to avoid WAR and WAW hazards while executing instructions, how can we know that there is no need for a physical register anymore and we can put it back in the free list?
1
vote
0answers
12 views

Single queue instruction issuing in computer architecture

I am working on this paper titled “the microarchitecture of superscalar processors by Smith and Sohi” and it says that there are 3 methods of organizing instruction queue. I know that the method “...
1
vote
0answers
76 views

Difference between Response time, Execution time, and CPU time

I studied Computer Architecture from David A. Patterson and have came across the idea of Response time. Response time also called Execution time. The total time required for the computer to ...
0
votes
1answer
45 views

How to calculate a direct mapped chace capacity with tag and valid bits?

I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course. Consider a ...
0
votes
1answer
24 views

ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
0
votes
1answer
29 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
2
votes
1answer
50 views

What is happening during “table walk”?

I am trying to understand what is a table walk. I have found when it occurs - whenever there is a TLB miss. If no descriptor is found – TLB miss occurs and further behavior depends on the ...
1
vote
3answers
66 views

Are all instructions eventually converted to zero-operand instructions?

Recently, my demonstrator said that all instructions are eventually converted to zero-operand instructions just before they get executed. yet another demonstrator said that this "doesn't make any ...
-1
votes
1answer
51 views

Computer Networks, OSI model

What layer of OSI model does define the route of information transmission between sender and receiver computers? A) Session layer B) Physical layer C) Data link layer D) Network layer E) Transport ...
0
votes
0answers
39 views

Data read vs instruction fetch

Why it is important for computer's security to differenciate between data read and instruction fetch memory access. As far as I know the processor have to know what is instruction and what is not ...
0
votes
1answer
29 views

Which address bits are used for set selection/tag check in a cache?

If Capacity = 24 KiB Associativity = 6 Line Size = 32 B As far as I know: $$Capacity = Associtivity * Line Size * Sets$$ so $24576 = 32 * 6 * Sets$ $Sets = 128 = 2^7$ thus 7 least significant ...
1
vote
1answer
49 views

Data hazard after in load word after addi

5 stage pipline addi $t1,$zero,0x30 lw $t2,0($t1) sw $t2,0xff18($zero) addi $t2,$zero,100 Question is to find hazards existing in the code and the answer is:...
0
votes
1answer
18 views

Curiosity on system device nomenclature - Gaussian Mixture Models [closed]

Would not know if this is the best SE website to ask, but I could not find anything better, especially because the answer might involve a fair amount of computer science (although this is an ...
0
votes
0answers
19 views

Associative cache finding the tag and word number

An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes. I'm unsure how to find ...
0
votes
1answer
24 views

Is the statement “Control unit controls overall operations of computer.” true or false

I was tutoring a grade 4 student about CPU and I got confused as there are also the other units of a cpu like arithmetic and logic unit and memory unit. So, is the above statement actually true even ...
0
votes
1answer
38 views

Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
-1
votes
2answers
28 views

Who decides that process needs cpu time or not?

I wonder how does particular process gets CPU time or resources whenever it's required to execute some instructions? When a process is in the idle state or waiting for input, it's not occupying the ...
0
votes
1answer
14 views

No. of disk blocks writes required for writing the file

Assume that a file is written using write(fd, buf, K) system calls, where fd is the file descriptor, and K, the number of files to be written to the current file offset which is a multiple of the disk ...
0
votes
1answer
27 views

Is OS mode required for accessing general purpose registers

In which of the following cases a process executing in user model is required to enter into the OS mode? (a) Decreasing the value of unsigned integer value in a register to less than 0 (b) Accessing ...