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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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3 sub part on Virtual Memory [on hold]

3 sub part on Virtual Memory. i need the solution as soon as possible please help me. thanks
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1answer
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If the Intel Pentium processors, was not made compatible to programs written for its predecessor, it could have been designed to be a faster processor

I find this question while solving some government job question bank. If someone could provide the answer along with a little explanation it would be very helpful. Ques:- If the Intel Pentium ...
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cache Hit rate and miss rate calculation one-way associative

I have this problem: A program that calculates the sum of 128x128 matrix of 32-bit integers (by rows). I have one-way cache that has 8 sets with block size of 64 bytes, considering only the access to ...
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3answers
81 views

How is an Assembly Language Processed by a CPU's Circuitry?

I'd like to have a bit more understanding of how, on a circuitry/hardware level, an assembler program works. I think I have a very broad-brush understanding of how a CPU would process machine code on ...
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1answer
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Compute cache miss rate for the given code

Problem Description: We consider a 128-byte data cache that is 2-way associative ($E=2$) and can hold 4 doubles in every cache line. A double is assumed to require 8 bytes. For the below code we ...
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1answer
24 views

Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
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16 views

Problem regarding caching. Block offset, Set index and Tag

I am currently reviewing for my exam in computer architecture. I've run into a question in the old exam sets that I can't really figure out. The question is regarding caches, more specifically block ...
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State-machine semantics of instruction set architectures

An instruction set architecture is an abstraction, a common interface layer between the software and the micro-architecture. The existence of this clearly delineated interface is becoming increasingly ...
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1answer
40 views

Doubt on Floating Point Representation [closed]

$1-2^{-23}$ and $2-2^{-22}$ both represents floating point representation or normalised representation.But are those two represent same value or both have different value? Is floating point ...
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How to determine index being access in memory

Having 4GB byte addressable main memory in 32-bit system divided into block of size 1024 bytes. If processor wants to access a memory location 0xFC347004. Corresponding block is found in cache. ...
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2answers
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In what sense are dataflow architectures non-deterministic?

The Wikipedia article mentions non-determinism in the context of dataflow architectures. Arthur Veen's paper mentions non-determinism when it elaborates on MERGE nodes as conditional constructs. Are ...
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1answer
14 views

Case where anti-dependency doesn't need pipeline stalling

While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling. But i couldnt find at example for ...
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What is tag-only forced cache inclusion called?

Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data? Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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1answer
151 views

What uses have been proposed for overlaid skewed associativity?

In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
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What is this weird gate?

This came from a picture of something that I'm supposed to make, and I can't find it in the program I'm supposed to use (LogicWorks). It looks like it 'not's only one of its inputs, but that doesn't ...
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1answer
34 views

Problem Set Solutions/Interrupts & Exceptions/Problem 1

Using Tomasulo’s algorithm, for each instruction in the listed sequence determine when (in which cycle, counting from the start) it issues, begins execution, and writes its result to the CDB. Assume ...
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1answer
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What architectural features will allow this microprocessor to access a separate “I/O space”?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition): Consider a hypothetical microprocessor generating a 16-bit address (e.g., ...
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2answers
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Why do we still use a Von Neumann Architecture in modern computers?

The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons. To this day the Von Neumann ...
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3answers
34 views

Program counter in a CPU

I know that the CPU has a program counter which takes instructions that are required to execute a program, from the memory, one by one. I also know that once the first instruction is executed, the ...
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How do I solve the part (a), of the following question?

The problem I'm facing is how do I know whether the mapping is "1-way set associative", "2-way set associative", "4- way set associative", etc. Please help!
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2answers
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Address bus and memory

If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it? What I'm trying to ask is that do all the 65536 locations ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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1answer
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Address and data bus

When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about? Also, why is the address bus unidirectional, as opposed to the data bus? ...
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1answer
61 views

Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it. Question was this: Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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58 views

Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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3answers
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Difference between RAM and buffer

I have searched but didn't get any exact difference between RAM and a buffer. If both are used for temporary storage, then why they are named differently while both having same property?
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Timing of Synchronous/Asynchronous Bus Operation

What is difference between Synchronous and Asynchronous Bus Operations. And how are they change in read cycle and write cycle ?? I shared a website it tells these bus operations bu I didint understand ...
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3answers
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Connection between CPU address bus and max amount of RAM

So, i'm stack on the following question > "A system has a 12 bit address bus. What is the maximum amount of RAM that can be installed on the system?" First of all, is this question correct? If so, ...
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1answer
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Is Carry Look-Ahead adder used in modern ALUs?

I recently came across carry look-ahead adder(CLA) in David and Sarah Harris's book(Digital Design and Computer Architecture). The circuitry for a 64 bit number (standard integer size in C) is ...
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1answer
81 views

Reasons for choosing register number and address sizes in an Instruction Set

Why would it be suitable to design an instruction set with 2-bits allocated for the register number and 10-bits allocated for the memory address? Would introducing a cache change this? (If possible I'...
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Why does Skillicorn's Taxonomy allow us to design 30 models?

In Skillcorn, David B, "A Taxonomy for Computer Architectures", IEEE Computer, 21(11):46-57, Nov 1988, a taxonomy of multiprocessor architectures is described. My teacher said that Skillikorn's ...
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2answers
324 views

What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
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3answers
51 views

Does increasing k in a k-way set-associative cache always lead to a better miss rate?

As far as I know a 2-way set-associative cache works better than a one-way one considerably but going to 4 and 8-way caches leads to a marginal improvement. My question is: does increasing K (going ...
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0answers
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CRC computation speed vs polynomials features

I tried to find information about how features of a CRC polynomials influence computation speed of implementations. It is obvious that (depending from the CPU architecture the algorithm runs on) ...
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How does computer work? [duplicate]

I am not a computer scientist or even a student of CS. I just want to find more information and would like if someone could put if in right direction about how actually computer works. I understand ...
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1answer
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The instructions a Stack Machine has

Trying to figure out which instructions a stack machine has, and wanted to clarify / reassure that these are in fact all of them. push onto stack ...
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2answers
62 views

If a NAND gate is universal, why you don't have NAND OISCs

If a NAND gate can be used to construct all other of the basic logic gates, then I'm wondering why you don't/can't have a purely NAND-based One Instruction Set Computer (OISC). All the OISC single ...
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0answers
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Minimum no. of flip flops for the given sequence

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of flip-flops required to implement this counter is________ According to me, the ...
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1answer
38 views

Examples of logic gates using non-standard models

These are the only ones I have been able to find online: Pulley Logic Gates Marble adding machine MARBLE COMPUTER LOGICAL AND GATE I would like to find some more discrete models like these (as ...
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1answer
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Maximum number of nodes connected when the link has a large buffer

A link of capacity 100 Mbps is carrying traffic from a number of sources. Each source generates an on-off traffic stream;when the source is on, the rate of traffic is 10 Mbps, and when the source is ...
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2answers
169 views

What is the avantage of having memory mapped I/O?

I can't make out what is the avantage of it comparing with the port designed I/O Is it faster? Is it more reliable? Is it cheaper?
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1answer
27 views

From where does the Fetch Unit get its instructions?

In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
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Do I need a implicit digit in a base-10 machine?

If I have a base-10 machine, Do I need a implicit bit or all numbers for mantissa take all bits? When I say bits, I mean digits. Since in a base-2 machine, You have a implicit bit. My question is if ...
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1answer
39 views

In which category is the supercomputer SUMMIT according to Flynn's taxonomy?

I have read that the POWER9 processor is an SIMD processor. I have also read that most supercomputers are MIMD based. So is the SUMMIT supercomputer SIMD? And if it is can you name a supercomputer ...
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From nand to numbers [duplicate]

My understanding is that computers are basically made of nand gates, and that all other gates, such as and, or, etc, can be made from nand gates. So far so good, but how do we get from nand gates to ...
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1answer
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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158 views

How would a CPU designed purely for functional programming be different?

CPU's are to an extent designed with in mind the software that people will write for it, implicitly or explicitly. It seems to me that if you look at the design of instruction set architectures, ...
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1answer
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If there is any sense of an optimal set of instructions in an ISA

So there are One Instruction Set Computers, having only one (complicated) instruction like addleq, "add and branch if less than or equal to zero". And then there ...
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3answers
112 views

How does a computer “wait” time?

Me and a friend were discussing how programming languages can perform asynchronous tasks, like waiting 15 seconds before performing another task, and we started a debate. I know that computers have ...
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How to find the definition of Computer Architecture terms in Compter Science? [closed]

To find the meaning of computer architecture terms in Computer Science do I need to use a Computer Science book? Do I need to find the computer architecture terms in a Computer Science Dictionary or ...