Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
932
questions
3
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1answer
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Under which conditions a given program is deterministic on x86_64 machines?
Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
0
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0answers
10 views
Do industrial automation PLCs have their own special purpose firmware or Instruction Set Architecture?
What is the ISA on the top of which the Programmable Logic Controllers run? Do they have one like in our personal computing devices having Intel x86, amd64 or ARM architecture for smartphones?
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0answers
22 views
Can someone explain to me the meaning of these messages in Computer Architecture
I am assigned a project in which I have to simulate a multiple level cache hierarchy and the messages exchanged between them. I have been given these following messages to take care of, but I do not ...
1
vote
1answer
9 views
Memory Invalidation and Misses
Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's ...
1
vote
1answer
42 views
Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?
Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years.
Or the frequent changing of smartphones has a ...
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0answers
6 views
How would I go about calculating the index field / tag field?
For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas?
Given a cache that holds 512 words and block size of one word. ...
0
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0answers
79 views
How would I calculate the cache hit rate (ratio) percentage?
If I am correct the hit rate formula is:
Hit ratio = successful hits / total requests... so would the question below be formatted as such:
I tried 4 entries / 8 memory accesses but that wasn't right ...
0
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0answers
13 views
How to compute the Cycles in a pipelined single cycle processor
I'm an undergrad studying computer engineering and I'm in my first of many courses on computer organization/architecture. In the lectures and online I see diagrams like the one pictured below from the ...
1
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0answers
38 views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
1
vote
0answers
20 views
Two Vs Dual Port RAM
Regarding the difference between Two Vs Dual Port RAM Here is what I understand:
The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
1
vote
2answers
52 views
Harvard processor structure
In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
0
votes
1answer
36 views
Why did Apple include dedicated a neural network “processor” in standard consumer products?
Not sure if this is the right place, but I guess it is better than Reddit and I couldn't find any discussion.
I was wondering why Apple include a neural network "processor" and can't help ...
0
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0answers
12 views
Help understanding main memory to cache block mapping
I'm currently self-learning on the cache memory and have come
across a method on how to find out which cache block a memory address will be
mapped to:
...
1
vote
2answers
40 views
Definitions of Computer Architecture and Computer Organization seems confusing
So there was this question in one of my class tests. It may seem very simple and straight-forward, but I am unable to catch up with its meaning or explanation. I have referred my textbook of COMPUTER ...
0
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0answers
18 views
Why return address may be lost and information in mask, processor registers may be ambiguous if an interrupt is acknowledged in following situation?
In the text Computer System Architecture (3rd Edition) by M Morris Mano , on pg. 415 under the section parallel priority interrupts I came across the following statements.
The bit in the interrupt ...
0
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0answers
31 views
What does “associative” exactly mean in “n-way set-associative cache”?
I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
-1
votes
1answer
27 views
Calculating the pipeline speed up in case we have an infinite amount of stages
I have the following question:
We begin with a computer implemented in single-cycle implementation.
When the stages are split by functionality, the stages do not require
exactly the same amount of ...
0
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0answers
21 views
Hardware implementation of direct mapped , set associative mapped and fully associative cache
I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
0
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0answers
12 views
If an instruction contains an address, how is it copied to the MAR?
Since the Memory address bus is unidirectional, how is an address copied to the MAR if a previous instruction such as "STO 150" contains an address? STO would store the contents of the ...
1
vote
1answer
89 views
Is there code below microcode?
Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
0
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0answers
13 views
Types of recordings on magnetic disks
Is my searching about the types correct?
Types of recordings on magnetic disks
Write: The current which goes through the coil produces magnetic field and then the pulses are sent to the head which ...
0
votes
1answer
17 views
Reference asking : High Performance Computer Architecture
Topics
Pipelining: Basic concepts, instruction and arithmetic pipeline, data hazards, control
hazards, and structural hazards, techniques for handling hazards. Exception handling.
Pipeline ...
0
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1answer
53 views
Is it possible to transmit bits digitally?
I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
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1answer
76 views
Find number of platters of a given disk
I am kinda blocked trying to figure out the answer to this question. Mind helping?
A manufacture wishes to design a hard disk with a capacity of 60 GB or more (using the standard definition of 1GB = ...
1
vote
1answer
57 views
Arithmetic on signed 12-bit octal number stored in sign magnitude form
What is 4365 ā 3412 when these values represent signed 12-bit
octal numbers stored in sign-magnitude format? The result should be written in
octal. Show your work.
Octal to binary:
4365: 100 011 110 ...
0
votes
0answers
14 views
I'm to calculate the tag, index and offset for a given setup
Total Memory size = 65,536 bytes
Number of cache blocks = 32 cache blocks
Cache size = total 512 bytes
So using this info provided I cannot figure out how to calculate the cache block number.
I know ...
0
votes
0answers
24 views
Loop Dependencies
Say I have loop like this,
for(1 to 10)
{
A[i][j]=A[i][j];
}
What kind of dependency is this? RAW or WAR?
According to me it is none, since there is no problem ...
0
votes
0answers
10 views
Original values of base and linkage pointer
When you first call a function, the first two commands in assembly are PUSH(LP), PUSH(BP) (BP = base pointer, LP = linkage pointer). What are the initial values of BP and LP?
For example, take pages 2-...
1
vote
1answer
41 views
Multiple correct answers for compilation
When you are asked to hand compile into assembly language, are there multiple correct answers? For example, in https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-...
2
votes
0answers
17 views
Output Dependency using Delta Test
Is there any way to find output dependency using delta test?
I know that we can perform flow and anti dependence test using delta test, but to find output dependency for such case?
For example say if ...
2
votes
1answer
21 views
Linear Speedup and Amdahl's law
I'm having trouble understanding and solving the problem.
Suppose we have a program which is composed of 3 portions A, B and C and that each portion takes $t_A$, $t_B$ and $t_C$ respectively to run on ...
0
votes
1answer
30 views
Little endian architecture,
Address 0000 stores 0xde
0001 stores 0xad
0002 stores 0xbe
0003 stores 0xef
Treat the data stored as 2 16 bit integers, what are the two values stored?
I thought the answer would be 0xadde and 0xefbe ...
-2
votes
1answer
19 views
How would I answer this? I recently started doing computer studies at school
is this format okay? this is my first time using stackexchange.
0
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0answers
12 views
Why cannot Operand forwarding remove all RAW hazards?
I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
0
votes
0answers
20 views
Risc-V extension for dismissible loads
Certain architectures have "dismissible loads" in addition to normal loads: when the load is denied, instead of issuing an exception (leading to a segmentation fault), a default value (e.g., ...
2
votes
2answers
39 views
What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?
I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
1
vote
1answer
24 views
How does virtual memory work when it need to save data in physical memory into disk?
I'm reading a textbook which desribe VM as:
a data structure stored in physical memory known as a page table that maps virtual pages to physical pages. The address translation hardware reads the page ...
1
vote
1answer
36 views
Cache Miss and Processor Speed
today in my class my professor mentioned that
Cache misses becomes more expensive as the speed of the processor increases
But he didn't explain the reason. I ...
-1
votes
1answer
45 views
Unsigned/signed boolean
Answer is c). I understand that the expression evaluates to true but what does signed/unsigned have to do with booleans?
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0answers
14 views
Is there any research on allocating memory across multiple non-contiguous regions?
From my understanding, malloc and-the-like allocate contiguous blocks of memory. It then returns to you the start address of the memory block.
This (and other ...
2
votes
1answer
53 views
Course teaching time complexities in real life systems
Having mis-read What course in CS deals with the study of RAM, CPU, Storage? I now wonder what course in CS deals with time and space complexities including GPUs, CPU caches in multiple levels, seek ...
0
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1answer
45 views
Is machine epsilon the largest relative error in representing a number as a floating point number?
Is machine epsilon the largest relative error in representing a number as a floating point number?
There are so many definitions of machine epsilon. I'm starting to get confused.
Isn't the machine ...
0
votes
1answer
37 views
Vectorization vs Asynchronous parallelism
I have taken a course "Programming for Performance" in my college and in the first week of the course, I have come across vectorization and Asynchronous Parallelism. But I am unable to ...
0
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0answers
17 views
A 32 ā bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips
A 32 ā bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh ...
0
votes
2answers
43 views
Storage in registers
Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
0
votes
1answer
42 views
memory storage of a program before compiling
Whenever we write code, after compilation the code will be converted to machine language and then stored in the hard disk. But before compiling the code, it is still in the high-level language. How ...
0
votes
1answer
100 views
Booth's algorithm Question : Binary Number Arithmetic (Multiplication)
It's being said booth's algorithm produces the output exactly as normal binary multiplication while reducing the number of operations performed and can be used for both positive and negative numbers !
...
0
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1answer
61 views
How can I mathematically show the largest possible value of a 64-bit double?
I'm a physics student wondering how I can mathematically show the largest possible value of a 64-bit double. I don't want to know just the answer, since that is freely available. The equation I was ...
2
votes
3answers
63 views
Do the newest computers still have ROM?
Now that many computers use UEFI instead of BIOS to boot the computer, and UEFI instructions are usually stored in a hidden hard disk partition, does this mean the newest computers do not need to have ...
0
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0answers
7 views
Data Hazards and stalls
I am studying for my exam tomorrow and I am having difficulty in the below code :
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
Due ...
