Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Pipeline throughput = 1/MAL*τ. Derivation

Pipeline throughput = 1/MAL*τ How do we get this formula. Can someone please show its derivation?
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Cache consistency in uniprocessor system

In a uniprocessor system, can we have a Cache consistency problem? For sure, it exists in a multiprocessor system. But I wonder if it exists in a uniprocessor system and in which scenario.
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Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
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Difference between multiprocessor and uniprocessor in terms of run-time system

In the book "Advanced computer architecture and parallel processing" (El-Rewini & Abd-El-Barr), there is a question in the exercises of chapter 1 that needs the reader to compare between ...
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how does the program change the clock speed of the processor?

bios is a program that checks all devices and starts the bootloader. but how does the CPU sync with the motherboard if the CPU clock settings are stored in the BIOS? Does the BIOS have CPU clock ...
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The following problem Decidable? If a Turing Machine M, on input w, will M ever move its read/write head to the left? [duplicate]

Decidable? If a Turing Machine M, on input w, will M ever move its read/write head to the left? I think the problem is decidable. We simulate M for |w| steps. Either it has moved to the left (accept) ...
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How is conditional jump implemented in the CPU?

After reading the question I'm still not sure how CPU does branching. I understand that we have an instruction counter which points to the current instruction. And after performing conditional jump it ...
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Negative Numbers in 32 bit Floating Point IEEE Numbers

So I understand the logic behind converting positive decimal numbers to IEEE 32 bit floating numbers but I'm not completely sure behind the negative one's. If for example we have a decimal number say -...
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The language accepted by the one-tape Turing machine where the input word is delimited by special symbols is decidable

My logic is that if the language accepted by such a device is decidable then the machine must halt by either accepting or rejecting the input. Let M be such a Turing machine, and we reject if M is in ...
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Classify as Regular, Decidable, or Acceptable

Classify it as regular, decidable, or recursively enumerable. Give the smallest class to which the language belongs. Can you correct my responses to the following questions? {x belongs to {a, b}* : ...
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What do “JAMZ”, “JAMN”, and “JMPC” stand for in Mic-1?

I am wondering what do JMPZ, JMPN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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Adding two numbers in base 2(floating point) vs Multiplying two numbers in base 2(floating point)

Is it true that adding two numbers in base 2 is more complex than multiplying them? If so can someone please explain why this is the case?
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When the stall is actually going to happen?

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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Effective Address for LDI instruction?

The effective address for the LDI instruction is the contents of the nearby memory location determined by the PC-Relative addressing mode. Let's assume that the address 0x5011 contains 1010 100 ...
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About NOP (NO Operation) for LC-3 instructions

0000 111 000011000 Will this instruction fail as a NOP? I think it is because it branches PC to a new address (incremented PC + 0x0018). If it were a branch that branches PC to itself like 0000 111 ...
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Select where the source operands are located for the following two LC-3 instructions:

Select where the source operands are located for the following two LC-3 instructions: 0001 111 010 0 00 011 1010 010 110011110 For source operands located in memory, distinguish the addressing mode ...
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Can old hardware be practically useful for CS problems of modern day?

Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
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How many cycles required in Instruction Level Parallelism?

L1: LD F1,0(R2) L2: LD F2,8(R2) L3: FADD F3,F1,F2 L4: SD F3,8(R2) If the instruction fetch for L1 starts at clock cycle 1, in which cycle the instruction L4 access memory to store the data? I am ...
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What percentage should be parallelized?

While exploring about the 2-core system. The voltage decreases linearly with the frequency. The voltage may not decrease below 75% below the original voltage.This voltage is referred to as the voltage ...
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Can x86 Instruction Set be changed with microcode update?

How I understand microcode translate an instruction to microinstructions. And CPU has a unit that stores all possible of microinstructions. These microinstructions can be changed, because it load ...
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How to calculate (physical address, tag bits, block index, cache index dan block offset) [duplicate]

i want to know how to calculate computer system with byte-address has a memory of 235. If the number of lines in the cache is 4096 lines and the block memory size is 16KB, and the mapping uses Direct ...
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How does a computer direct the processing of information

So I'm reading Introduction to computing systems:From bits and gates to C and beyond, and the author states that a CPU is the mechanism that ...directs the processing of information. Which is ...
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How to approach a problem on Amdahl's Law?

A processor design team is given the task to decide on a new variant of a multi-core processor that is allowed to use more silicon area but keeps the clock frequency and external interfaces of the ...
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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What is combinational circuit?

I'm reading the Digital Design and Computer Architecture by David Harris, Sarah Harris. The authors give the following definition of combinational logic: A combinational circuit’s outputs depend only ...
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Power8 addressing modes

I want to understand what are addressing modes that can be used in IBM Power8 microprocessors. In Pdp 11, Most operands can apply any of eight addressing modes to eight registers. But how having 124 ×...
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How do I compute the power consumption of a DRAM refresh?

Given a DRAM-based memory system with a total capacity of $x$ bytes, $y$ DRAM rows and a refresh time of $t$ milliseconds, how do I compute the power consumption for one DRAM refresh? I couldn't find ...
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Can a single core processor be MIMD?

I was wondering for if a single core processor can be MIMD? or MISD? or SIMD? I thought MIMD's requirement is multicore, but I am not sure about this
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Min number of register without spilling

The program below uses six temporary variables a, b, c, d, e, f. a = 1 b = 10 c = 20 d = a+b e = c+d f = c+e b = c+e e = b+f d = 5+e return d+f Assuming that all ...
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When can a deterministic finite-state-automaton (DFSA) along with its input sequence be said to be a part of another DFSA?

For a Finite State Automaton / Finite State Machine (FSM) $F$, that has an input alphabet, a set of possible states, an initial state, a set of possible final states and a state transition function, ...
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Interesting Speedup & Amdahl's law problem

I have found a problem on my Computer Architecture textbook which I have some issues with: We have a process which spends its time in the following way: 50% of the time, it executes common ...
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How do computers *really* work? (at the most basic level)

While learning about computers I will read about RAM and Storage and the CPU, and while these explain the architecture of a computer and how parts of a computer work together, I still don't understand ...
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About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor. We do assume that ...
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What will a given CPU architecture do in the event that we were to invert all of the instruction bits to a given instruction?

Given an arbitrary CPU - Architecture and its instruction set... What would be the outcome of the given inverted instruction within that Architect? For simplicity, let's use an 8-bit CPU architecture ...
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Representation of unsigned integer on a little endian, big endian computer

This is a GATE 2021 exam question. If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices ...
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K-Map Reduction Grouping Question

I have a simple question regarding reduction using K-Maps. My professor gave this example: While I somewhat understand that we can only group quantities of base 2 numbers, why did my professor group ...
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How to do -8 x -8 in a 4 bit booth multiplier?

In the general case of an n bit booth multiplier, the maximum negative value is -2n-1. So with 4 bits we can represent -8 x -8 (M=1000, Q=1000). Now if we follow Booth's algorithm for multiplying n-...
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Which has optimum performance? raw core or multithreaded

Let's say there's a single process performed in the machine which utilizes all available processors (whether physical or logical processors). The process use 100% processor utilization most of the ...
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How does Instruction Set Architecture (ISA) affect performance?

If 2 CPUs have the same Instruction Set Architecture, which of the following properties will be the same? Clock Rate CPI Execution time No. of instructions MIPS
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How was von Neumann's architecture turned into a parallel capable architecture and is there any limitations to that?

Back when von Neumann came up with his computer architecture parallel machines and multi-core processors weren't a thing but now almost all machines have multiple cores and are able to run programs in ...
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Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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How do I compute the address of the next element?

I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
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Metrics on which Clock Cycles Per Instruction(CPI) depends

In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this: The term clock cycles per instruction, which is ...
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Must a Turing machine tape be binary?

I once asked why does computer data bits are usually organized on binary (base 2) sets, rather than on unary (base 1) sets, aiming to also understand why its not also ternary (base 3), heptary (base 7)...
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Minimal number of resources such that the system is considered safe?

In a system with a single type of resource, there are 8 processes with the following maximal requirements: Process P1 P2 P3 P4 P5 P6 P7 P8 MAX 75 60 65 35 30 45 30 30 Specify the minimal value for ...
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Why do register machines outperform stack machines?

Wikipedia says stack machine “designs have though been routinely outperformed by the traditional register machine systems, and have remained a niche player in the market.” Why is this?
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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How Can We Classify Summit Supercomputer in Terms Of Topology

Summit supercomputer has Processor: IBM POWER9 22C 3.07GHz Interconnect: Dual-rail Mellanox EDR Infiniband. So how can we classify in terms of topology? How can I find resources about this subject?
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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What is the difference between speculative execution & branch prediction?

In computer architecture I'm confused between speculative execution & branch prediction. Are the same or different?

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