Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
824
questions
0
votes
0answers
7 views
%var% reach 0 and needs to jump a segment [closed]
So I need %var% when it reaches 0 to jump to a code segment
I have tried:
Set /a gold=%gold%-500
If %gold% LSS '0' goto a
Set /a gold=%gold%-500
If %gold% == '0' goto a
Set /a gold=%gold%-500
If %...
0
votes
0answers
6 views
How to send data from local host to Online server [closed]
I working on a project which is saved data on local host when internet connection not connect , if internet connection available when these all data on local host automatically send to Online server. ...
0
votes
1answer
17 views
Operating System code suffers more cache misses than user code
I was going through the text of the book Computer Architecture: A Quantitative Approach. It has a section in Chapter 5 where it discusses the fact that OS code undergoes more cache misses as compared ...
0
votes
0answers
63 views
Power of Supercomputer, 3 to the 48
Can a supercomputer do $3^{48}$ computations within 3 days, say?
I would appreciate any help.
0
votes
0answers
29 views
Which of these devices might speed up processor?
I have test question.
Which devices inside processor are used to speed up work indirectly
i.e. program isn't executing a code for that device?
Possible answers: DRAM | Cache | Pipeline | GPU | ...
0
votes
0answers
24 views
Is it possible to run more than one Turing Machine emulator using only one processor kernel?
I had this question on computer architecture exam and can't find an answer anywhere.
Is it possible to run several Turing Machine emulators at once using only one processor kernel?
a) Yes, by ...
0
votes
1answer
30 views
Understanding How Double Precision Numbers are Stored in a Computer
I am reading Numerical Analysis by Walter Gautschi. I am somewhat confused by the following quote from page $5$:
To increase the precision, one can use two machine registers to represent a machine ...
3
votes
1answer
121 views
How does a GPU get data from a CPU?
From what I’ve read, the CPU has to send the data to the GPU before the GPU can do anything with it. But, if that’s the case, won’t any time saved using the GPU be negated by the time taken to ...
1
vote
1answer
24 views
How many RAW dependencies are present in these instructions?
What is the number of RAW dependencies in below set of instructions?
I1: R1 = R2 - R3
I2: R2 = R1 + R3
I3: R3 = R1 + R2
I4: R1 = R2 - R2
I can see the following ...
0
votes
0answers
60 views
Deep pipeline - cpu architecture
I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance.
While reading about vector instruction, I encountered the term deep ...
4
votes
0answers
35 views
Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?
In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
3
votes
1answer
34 views
Is PREFETCH an asynchronous operation?
I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
0
votes
0answers
118 views
1
vote
0answers
31 views
Can differennt computation model lead to different complexity?
There are many examples where someone replaces a CPU with a GPU or an FPGA and get a performance boost of $\times 100$ or more, but is it possible for a change in the architecture of computational ...
1
vote
1answer
27 views
Being a computer organizations and architecture expert
One of the greatest challenge in learning one is how broad the literal computer science is. Just talking about memories and CPUs would just took you to endless adventure of this technology. How does ...
0
votes
0answers
42 views
A question about Pipeline Cycle
This is my question, I am so confused with my answer, looking for help!
This is my answer:
Explanation: At the third instruction, instruction is waiting before ID, thus, no stalling is needed. (it ...
0
votes
0answers
27 views
how worst fit better than best fit?
I am a beginner. I have recently started studying OS.
In textbook, it is written as best fit is worse than worst fit. Reason - external fragmentation.
IMO,in case of variable partionioning, best ...
2
votes
1answer
32 views
doubt in pipelining
I am not from cse but trying to learn computer architecture on my own. Please clarify the following.
In case of pipelining, each stage or subcomponent or subtask is assumed to be done in 1 CPU ...
0
votes
0answers
26 views
Associative mapped cache, word addressable
I have an associative mapped cache with 10 tag bits and an offset of 7bits.
What is the size of each main memory block in words(word addressable) and main memory size in words?
i worked it out as:
...
1
vote
1answer
52 views
What is the difference between a microoperation, microinstruction and control word?
I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
0
votes
0answers
8 views
Study of cache behaviour of algorithms on Virtualbox
I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general.
I want to understand, is it advisable, if I do this study in an virtualized ...
0
votes
0answers
9 views
Are there any models of operating systems which don't require rings of privileges, that are also secure?
I am working on a simple operating system in JavaScript and have noticed that there are two kinds of processes: the "main" process (or "kernel" process), and all the other processes. Basically they ...
0
votes
1answer
30 views
What happens with register usage in deeply nested functions calls (in theory)?
I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
1
vote
3answers
72 views
How many registers does a computer *need*?
I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
0
votes
0answers
10 views
Relationship between associativity, number of sets, block size and cache inclusion policy
I'm studying for an exam and I came across a couple of questions asking me to argue whether cache inclusion is guaranteed or not. I read Wikipedia and wikipedia claims cache inclusion is possible if ...
1
vote
2answers
30 views
How does a CPU differentiate between 1-operand instructions and 2-operand instructions?
Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction ...
2
votes
0answers
23 views
Compiler optimization which does an SMT-like optimization in software?
Say I had two functions called one after the other:
...
2
votes
3answers
80 views
Is the constant pi (not Raspberry) ever used in general computer science?
Is the constant pi (not Raspberry) ever used in general computer science? If so, how so or when is it applicable?
1
vote
0answers
9 views
Approximate cache size & cache line size from optimal tile size
I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
0
votes
0answers
44 views
Little Endian vs Big Endian?
Suppose a processor uses the big endian representation and x is a 32-bit integer stored in memory starting at the memory address 1000. The memory is byte-addressable, each location holding a byte. ...
0
votes
1answer
27 views
Read and write ports in a register file?
How many read and write ports in a register file? Moreover, what is the difference between a register and a register file?
0
votes
1answer
47 views
What is memory model in computer organization?
I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking ...
1
vote
0answers
30 views
Relation between CPU cycle and Addressing modes
Professor has given this question in exam. I am not able to find relevant reference for this question
Which Addressing Modes (for x86 architecture) consumes more CPU cycle?(Consider all are special ...
1
vote
0answers
30 views
What are the smallest and biggest negative floating point numbers in IEEE 754 32 bit?
I am stuck with a question that asks for smallest and biggest negative floating point numbers in IEEE 754 32-bit (their representation and decimal numerical value from which one can approximate the ...
0
votes
0answers
12 views
What is the use of relays in Harvard mark 1 (early electromechanical computer)?
First when I came to know that Harvard mark 1 had relays I thought that the relay were used like today's transistors for the purpose of processing. But I came to know that Harvard mark 1 had 5hp ...
0
votes
1answer
34 views
Can a new company make a processor compatible with Windows and current software? [closed]
Would anyone apart from Intel and AMD ever be able to make a processor that can be used on a personal computer, or is it impossible? I believe it is due to them owning the x86 instruction set, which ...
0
votes
0answers
32 views
Is 'the bombe' technically a computer?what is technically meant to be a computer?
Some say that 'the bombe' created by Alan Turing is technically not a computer despite decrypting the codes.
Why is it so? Is 'the bombe' technically a computer?
First of all what is technically ...
13
votes
2answers
6k views
What is a GPU year?
I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years".
What is a GPU year? How long is that?
0
votes
0answers
23 views
pipeline processor timing charts and total cycles
There are basically 2 things i need to figure out.
Timing charts
Total cycles for the 3 mips instructions.
How does it differ when it is branch taken and branch not taken for a "predict not taken ...
0
votes
0answers
15 views
Having trouble understanding the use of a label in Assembly
I am currently having trouble understanding what this label means in Assembly as it has no variable size with it. In the following program that declares several variables in the stack offset the ...
0
votes
0answers
35 views
How to create a register from DFF bit components?
I am a new student at computer architectures and my current task is to create a register of 4 bits.
We were a working DFF and my bit component seems to work.
My DFF:
My bit:
I tried to create the ...
1
vote
1answer
47 views
What is a sticky bit in computer architecture?
I am reading about a counter implementation in RISC Architecture. The specification reads,
Sticky overflow bit is set when the counter wraps through zero.
I can infer that the overflow bit is ...
0
votes
1answer
50 views
Lack of Stack Pointer Register
Suppose a processor lacks STACK Pointer Register. But, It does have STACK.
Then, in my opinion, a program will still be able to call subroutines but, will be unable to return back from the subroutines....
1
vote
3answers
75 views
How can any non-primitive-recursive function like the Ackermann function be implemented on hardware?
If for-loops and function calls both boil down to jump instructions when implemented on a real machine, then how is "The Ackermann function isn't implementable with for-loops" a meaningful phrase?
1
vote
0answers
40 views
L1 Cache Missing Timing Attack
I'm trying to understand Section 3: L1 Cache Missing in the paper Cache Missing for Fun and Profit. I'm stuck on trying to figure out how the covert channel is ...
0
votes
5answers
289 views
How does the computer know whether an address contains an instruction to be executed, or data to be used in an instruction?
The question is already stated in the title.
0
votes
0answers
14 views
Compare the difference in bus transfer times
Suppose we are given a 2-byte-wide bus that supports single-byte, dual-word (same clock cycle) and burst transfers. The overhead of the single-byte or dualbyte transfer is 1 clock cycle. Now we want ...
1
vote
0answers
28 views
Doubts on Virtually Indexed,Physically tagged Cache
I tried referring a few material (videos on youtube and this link as well), but I still couldn't wrap my head around the concept.
My (brief) understanding of the Virtually addressed, Physically ...
0
votes
1answer
87 views
Least Significant Bit (LSB) vs Little Endian - Are they equivalent in anyway!
For a multiple choice question: What do we call the LSB?
(i)Little Endian (ii)Upper bit (iii)Big Endian (iv)Lower Bit
I feel ideally none of them is a true correct choice, but my best bet was (...
1
vote
0answers
48 views
Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa [closed]
Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa in floating point notation or otherwise. We actually have to prove this is not possible. But why can't we if we have infinite ...
