Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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Getting started with computers
I started to learn how to create apps and realized that I want to study computers more deeply but I don't know where or how to start. Could you please help me with some helpful resources for studying ...
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1answer
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Should a solid state hard drive make crunching work noises?
I use heavy software. 3d, mostly. I'm used to the comforting sound of a hard drive that sounds like a popcorn popper.
But, just got my first Lenovo, with a solid state hard drive. Model KXG6AZNV512G ...
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Will learning about integrated circuits, help me be a better computer architect(long-term)?
I do not know if this is the right place to ask this type of question, but here I go, im thinking about learning integrated circuits as part of learning more about computer hardware in general (but ...
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What is “orthogonality” in the context of Instruction Encoding?
What does it mean by "orthogonality" in the context of Instruction Encoding?
Why CISC Architecture is orthogonal while RISC is not?
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How fast can 10 integer multiplications be executed?
This is self study, but not homework. I am reviewing some slides I found online and have come across the following question.
Question:
If the latency of integer multiply is $3$ and the cycles/issue ...
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Can someone in Cyber Security or IT help answer this basic question on the change of today's malware? [closed]
1.) Before the most common types of malware were usually trojan horses and various other types of viruses derived from one’s own e-mail on a desktop. Given the timespan since those days, the game has ...
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Minecraft Computing
Basic computers have been created and optimized several times before in Minecraft. These were based on logic gates constructed from the 'redstone torch' block. I (who knows little of computers) was ...
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1answer
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Why the Call instruction in the x86 architecture saves the return address as EIP+5 instead of 4?
In 'The Computer Organization and design book' it illustrates the call instruction as
Decrementing the stack pointer by 4.
saving the EIP+5 into the stack.
Jumps to the new address specified.
What ...
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2answers
50 views
how pseudo direct addressing works?
In pseudo direct addressing mode (For the MIPS architecture) the 26 bit of the jump instruction are joined to the upper 4 bits of the PC .
how could this help in jumping to relative positions suppose ...
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1answer
27 views
What does it mean to isolate a field in a word?
I have been reading in the 'computer organization and design' book and I encountered this section:
what operations isolate a field in a word
I know that the ...
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1answer
28 views
Bus and System Clocks
What is the difference between a Bus clock and a System Clock? Do they function the same way? I have been reading about System clocks but I can't really find anything about bus clocks in my book to ...
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Amdahl's Law and efficient algorithms
Does the efficiency of algorithm leading to better performance of the system can be attributed to Amdahl's Law?
or
Is the Amdahl's law only applicable for the analysis of efficient hardwares and ...
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Preparing for midterm exam. Please help with below problem
Select all techniques that are helpful for
① Hardware speculation ② Compiler speculation ③ Software pipelining
④ Tomasulo's algorithm ⑤ Scoreboarding ⑥ Forwarding
⑦ Delayed branch ...
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1answer
42 views
How does the hardware of a while loop work?
I know get how logical operators for if logic gates work, but I am trying to understand how while loops fit into that picture. I realize that this question is a bit vague. It all started because I was ...
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1answer
41 views
Machine has 64 bit architecture and two word long instruction
A machine has a 64-bit architecture, with 2-word long instructions. It has 128 registers, each of which is 32 bits long. It needs to support 49 instructions, which have an immediate operand in ...
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Does Nand Flash Type Affect the Read Latency Based on Page Content?
In general, we have these types of NAND flash cells: SLC, MLC, TLC, and QLC. Since MLC flash cells can store 2 bits, the content of the cell can be 00, 01, 10, or 11 which are detected using different ...
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1answer
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Full adder carry expression
I'm learning about logic circuits and I've come across full adder. In the book they derived its two carry out expressions -
Cout = x&&y || x&&z || y&&z
and
Cout = x&&...
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Where is the register position in a CPU (real image illustration)?
I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
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service demand in the topic of distributed systems
I am so confused about this question , imagine we have a disk that the service demands of database transactions on this disk is 0.1 sec , additionally we increase the disk speed by 40% so how service ...
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Linker question in MIPS
The above is the example from section 2.12 Translating and Starting a Program from Computer Organization and Design, Fifth Edition, The Hardware/Software Interface, by David A. Patterson and John L. ...
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13answers
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What are GPUs bad at?
I understand that GPUs are generally used to do LOTS of calculations in parallel. I understand why we would want to parallelize processes in order to speed things up. However, GPUs aren't always ...
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1answer
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How to Calculate Clock Rate for Processor?
Please can anyone help me to solve the following question, I have no idea to solve that 👀.
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1answer
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what is the difference between an adapter and a controller?
1- why do have a USB controller but a display adapter ?
2- I have heard the terms network adapter and network controller being used, is there a differance between those ?
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Google's TPU peak performance
Google's TPUv1 comprise 256x256 MACs and runs at a frequency of 700MHz.
Therefore, the peak performance is
$$
(256\times256)\cdot 700 \text{MHz} = 46 \text{TOPS/s}.
$$
Yet, everywhere they mention ...
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1answer
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Can a 32-bit processor work with a 64-bit size word?
In a 32-bit byte addressable memory system, each "row" has 4 bytes and each byte has a 32-bit address.
My question is: can I read and/or write word of length 64 bits from/to memory?
In other terms, ...
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24 views
Is there any kind of secure computer system on the horizon?
I'm going to attempt to be as concise as possible, given this highly complicated subject. However, some basic things need to be said here to properly "paint the picture", so kindly don't see it as a "...
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2answers
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Do we need to check for mantissa overflow in floating point multiplication?
We do check for the mantisas overflow in floating point addition
e.g.
If we are adding $8.02 \times 10^3 + 9.01 \times 10^3 =17.03 \times 10^3$ i.e we get an overflow, so we shift the number right ...
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1answer
21 views
Operating System code suffers more cache misses than user code
I was going through the text of the book Computer Architecture: A Quantitative Approach. It has a section in Chapter 5 where it discusses the fact that OS code undergoes more cache misses as compared ...
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Is it possible to run more than one Turing Machine emulator using only one processor kernel?
I had this question on computer architecture exam and can't find an answer anywhere.
Is it possible to run several Turing Machine emulators at once using only one processor kernel?
a) Yes, by ...
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1answer
37 views
Understanding How Double Precision Numbers are Stored in a Computer
I am reading Numerical Analysis by Walter Gautschi. I am somewhat confused by the following quote from page $5$:
To increase the precision, one can use two machine registers to represent a machine ...
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1answer
135 views
How does a GPU get data from a CPU?
From what I’ve read, the CPU has to send the data to the GPU before the GPU can do anything with it. But, if that’s the case, won’t any time saved using the GPU be negated by the time taken to ...
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1answer
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How many RAW dependencies are present in these instructions?
What is the number of RAW dependencies in below set of instructions?
I1: R1 = R2 - R3
I2: R2 = R1 + R3
I3: R3 = R1 + R2
I4: R1 = R2 - R2
I can see the following ...
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Deep pipeline - cpu architecture
I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance.
While reading about vector instruction, I encountered the term deep ...
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Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?
In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
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1answer
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Is PREFETCH an asynchronous operation?
I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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1answer
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Can differennt computation model lead to different complexity?
There are many examples where someone replaces a CPU with a GPU or an FPGA and get a performance boost of $\times 100$ or more, but is it possible for a change in the architecture of computational ...
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1answer
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Being a computer organizations and architecture expert
One of the greatest challenge in learning one is how broad the literal computer science is. Just talking about memories and CPUs would just took you to endless adventure of this technology. How does ...
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A question about Pipeline Cycle
This is my question, I am so confused with my answer, looking for help!
This is my answer:
Explanation: At the third instruction, instruction is waiting before ID, thus, no stalling is needed. (it ...
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how worst fit better than best fit?
I am a beginner. I have recently started studying OS.
In textbook, it is written as best fit is worse than worst fit. Reason - external fragmentation.
IMO,in case of variable partionioning, best ...
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1answer
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doubt in pipelining
I am not from cse but trying to learn computer architecture on my own. Please clarify the following.
In case of pipelining, each stage or subcomponent or subtask is assumed to be done in 1 CPU ...
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Associative mapped cache, word addressable
I have an associative mapped cache with 10 tag bits and an offset of 7bits.
What is the size of each main memory block in words(word addressable) and main memory size in words?
i worked it out as:
...
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1answer
168 views
What is the difference between a microoperation, microinstruction and control word?
I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
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Study of cache behaviour of algorithms on Virtualbox
I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general.
I want to understand, is it advisable, if I do this study in an virtualized ...
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Are there any models of operating systems which don't require rings of privileges, that are also secure?
I am working on a simple operating system in JavaScript and have noticed that there are two kinds of processes: the "main" process (or "kernel" process), and all the other processes. Basically they ...
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1answer
31 views
What happens with register usage in deeply nested functions calls (in theory)?
I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
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3answers
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How many registers does a computer *need*?
I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
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Relationship between associativity, number of sets, block size and cache inclusion policy
I'm studying for an exam and I came across a couple of questions asking me to argue whether cache inclusion is guaranteed or not. I read Wikipedia and wikipedia claims cache inclusion is possible if ...
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2answers
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How does a CPU differentiate between 1-operand instructions and 2-operand instructions?
Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction ...
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Compiler optimization which does an SMT-like optimization in software?
Say I had two functions called one after the other:
...
