Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Can computers design computers?

Hello I hope this is the correct forum for the question. Maybe is a silly question. I hope not. The machine instructions set of common computers comes from the age when people wrote programs in a ...
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Alu architecture of a Hack Computer

I'm currently studying the ALU architecture (of a Hack computer) and how it works. As part of my assignments, I have been asked the following question: If we want the ALU to compute the function y-1, ...
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Is it possible to build a computer whose "ALU" is a single NAND gate?

I am not asking about if it is possible to build a computer using only NAND gates, since that question has been asked infinite times. I wonder if it is possible to replace the “ALU” in the cpu of a ...
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Can there be a computer without software (only hardware)?

Can there be a computer without software (only hardware) which can produce meaningful output? "Software" would be for example an operating system (whether in the level of "firmware&...
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What are the width of data/control/address bus for a 32-bit CPU?

Are they exactly 32bits for a 32-bit CPU?
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How can DRAM memory speeds be improved?

What are some ways with which we can improve the speed of dynamic RAMs?
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What are the chances of fusing a quantum computer and a parallel computer and what potential dangers/ benefits does it bring?

From my EPQ research I came to know that quantum computers require certain conditions to function optimally such as: low temperature so that electrons do not get disturbed etc. I've also read a book ...
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Where does tag directory is stored

I am studying direct mapping in cache. I understood the concepts like dividing into blocks and lines , tag directory etc. When solving numerical problems of finding main memory size or tag directory ...
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8085 microprocessor connection of CPU data bus with RAM data bus

What would happen if the CPU data-bus bit 2 is connected to the RAM data-bit 5 and CPU data-bus bit 5 is connected to RAM data bit 2? Assume the rest of the connections are all right – explain.
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Do number of registers and width of register have to be the same?

I am studying Computer Architecture with MIPS-32. The example system has 32 registers with each register having a width of 32 bit. If I would want 128 registers instead of 32 registers, would I have ...
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Would it be wrong to say that the processor (and hardware) is the implementation of an interpreter for machine language?

The question is basically in the title. I know that a computers hardware is of course some physical object, where as the interpreter is some abstract thing that does something abstract with the code ...
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What determines bus speed?

I would like to know what determines bus speed in a CPU. I know about bus width, that all makes sense, but since electrical pulses travel at light speed I don't understand why bus speed is measured ...
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What does 'single sequential computer' mean?

I'm from a non-technical background. (Mentioning this for the convenience of explanation w.r.t intelligibility) Book Name - "Introduction to Algorithms" Authors - Thomas H. Cormen, Charles E....
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity

Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
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Will we ever move towards 128 bit architecture?

Will the IBM PC ever move towards 128 bit architecture? Is that even possible or is the 64 bit architecture we have now the ceiling?
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Why does this branch data hazard happen during the instruction decode stage?

Suppose I have the following MIPS code on a CPU with forwarding enabled: ...
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Question about GPU workload dispatch and interconnect

there are very few materials about GPU architectures and how each of the GPU cores is connected in the SoC. I am quite confused on how in general the GPU cores are usually connected together, is it ...
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system architecture or software architecture

I was trying to get started with a small project but I quickly realized I had to do more research on the subject. Suppose, when creating a site, in production, there's a certain structure how the ...
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What are the major functions that are performed by CPU to handle the I/O devices?

I can't find the complete answer from browsing that's why I am asking. I found functions of IO interface. Is it the complete answer for this question? Hope I can get some pdf of website links from ...
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Where is actually ASCII is stored in computer?

I am learning some basics in computer. In that in ASCII I read if 65 is A . When we pressing key A what is happening next? Is the electric signal is passing as on & off & reaching to decimal ...
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Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
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What does it mean for a computer to be general-purpose?

There is a lot of Turing machine out there. Most of them are purpose-specific. What make universal Turing machine universal? How do we know or prove if a computer is universal? Edited: Is ...
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What kind of binary compatibility is present for 2 processors sharing an Instruction Set?

Consider Intel x86 and AMD x86 Processors. As I understand, since they use the same Instruction Set, in theory an application compiled for Intel x86 processor would run without any modification on ...
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Bus Bandwidth Calculations

I cannot understand this question and the model answer for it and I wonder if anyone here is able to help me. Question: ...
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In what stage is next PC address available or known to the processor?

Assuming you know the meaning of pipelining in Computer architecture & organization. When is the next PC address or jump address available or known to the processor? In this lecture, https://youtu....
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Memory Address Lines

I am reading a text book by David Tarnoff and there is something I do not understand, the section is on CPU and memory. The book states that the number of address lines going into a memory device ...
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Why did finite-state controller with datapath win?

I just finished watching the 1986 SICP lectures, and the concepts are rolling around in my head. My question: why is "finite-state controller with datapath" the implementation of computer ...
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What would happen if while making a connection between memory and CPU, the address lines get's interchanged

While making a circuit connection between Micro Processor and Memory Chips, the Address Lines A0 and A1 got interchanged. Means A0 of address bus got connected wrongly with A1 of Memory chip and A1 of ...
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How does software prefetching work with in order processors?

From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching: ...
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logic and communication technicalities between computer components

Concerning modern computers communicating with each other it is my understanding that computers are reading patterns in current flow and interpreting those patterns of current flow as ours 1's and 0's....
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Cache coherence is worthless and does nothing?

When you perform a write on a multi-cpu system, relevant cache flushes are done to ensure that the other cpus see the change immediately. BUT That write was issued from an independent thread on a ...
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Understanding IBM370 Relaxed Memory Consistency

In the report "Shared Memory Consistency Models: A Tutorial" (https://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf), the authors explain the difference between IBM370, Total Store ...
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Average Access time in caches

I know that the average access time for systems with level 1 caches is: Average Access Time = Hit time + (Miss Rate x Miss Penalty) How can this be generalized for n level caches?
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Assembly Language Step By Step: Why deviate from the norm and design computers where the presence of voltage encodes a 0 bit?

That the presence of voltage across a switch encodes 12 is purely arbitrary... Jeff Duntemann's book mentions: We could as well have said that the lack of voltage indicates a binary 1 and vice versa (...
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Why does CLRS refer to the disk parts as pages rather than blocks?

I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters: In order to ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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What is the maximum memory address space that microprocessor can access directly if a 16-bit memory module is interfaced with a 32-bit microprocessor?

The Complete question is as follows : Consider a single-address 32-bit microprocessor with 32-bit address bus and 32-bit data bus. Its instructions composed of 1-byte opcode and 3-byte operand address....
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What is a forwarded clock?

I'm reading the overview book of the Intel QuickPath Interconnect and it says there: The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a ...
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Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
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How to determine the bits of the address used to access the cache?

Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a ...
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Interrupt enabling and disabling

While reading about interrupt mechanism, I understood that there is an IRQ signal line on the bus by which an I/O interface raise an interrupt request. There is an INTA signal line using which the ...
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Finding Worst and Best Case Hit Rate of a Cache Given Code

I'm doing some practice problems to study and came across this one: Consider a 8-way set associative cache with 64 B blocks, and 64 total blocks as part ofa 16 bit physical address. Imagine we use the ...
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Why is programmed I/O not suitable for high-speed data transfer?

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
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Can synchronous data transfer be used for transferring large data in case of computer architecture and organization?

I am learning computer architecture and organization. I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization? I ...
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Transactional memory

I would like to understand what role does Transactional memory plays in memory organization, I know that To allow for more efficient parallel programming with higher performance, processor implements ...
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How does virtual and physical memory affect cache structure?

Working with a question that states: Consider a hypothetical machine in which physical address space is of 512 words and virtual address space is of 2048 words. The page size is 8 words. What is ...
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Speed of a microprocessor

I was just wondering why are are new generation microprocessors faster at the same clock speed as the old ones. For instance a 2.66Ghz dual core i5 is faster than the a device with clock speed of 2....
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Manipulating stack pointer in assembly

I have written an assembly program to store digits in a stack. And to print the digits I have used loop2: mov ah,2 int 21h sub cl,1 jnz loop2 But this would only ...
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Dividing EX stage of a pipeline into EX1 and EX2 stages

There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be: In the five stage pipeline with forwarding support to EX, the first operand of ALU ...

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