Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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1answer
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How to calculate a direct mapped chace capacity with tag and valid bits?
I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course.
Consider a ...
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1answer
17 views
ARM STM instruction: page fault problem with MMIO
The ARM STM instruction is described here in the ARM manual.
This instruction writes all or a subset of registers at memory locations starting from a base memory ...
0
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1answer
24 views
jump to MMIO address
In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)?
Would this ...
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0answers
19 views
4-Way Set Associative Cache - which sets will be evaluated? [closed]
A computer has got a 4-way set associative cache.
4 Bit Offset
4 Bit Set
21 Bit Tag
The processor acces the memory adress 0x000164A2. Which sets will be evaluated in order to find a cache-hit?
2
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1answer
41 views
What is happening during “table walk”?
I am trying to understand what is a table walk. I have found when it occurs -
whenever there is a TLB miss. If no descriptor is found – TLB miss occurs and further behavior depends on the ...
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2answers
30 views
Are all instructions eventually converted to zero-operand instructions?
Recently, my demonstrator said that all instructions are eventually converted to zero-operand instructions just before they get executed. yet another demonstrator said that this "doesn't make any ...
-1
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1answer
39 views
Computer Networks, OSI model
What layer of OSI model does define the route of information transmission between sender and receiver computers?
A) Session layer
B) Physical layer
C) Data link layer
D) Network layer
E) Transport ...
0
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0answers
28 views
Data read vs instruction fetch
Why it is important for computer's security to differenciate between data read and instruction fetch memory access.
As far as I know the processor have to know what is instruction and what is not ...
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1answer
26 views
Which address bits are used for set selection/tag check in a cache?
If
Capacity = 24 KiB Associativity = 6 Line Size = 32 B
As far as I know:
$$Capacity = Associtivity * Line Size * Sets$$
so
$24576 = 32 * 6 * Sets$
$Sets = 128 = 2^7$
thus 7 least significant ...
1
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1answer
38 views
Data hazard after in load word after addi
5 stage pipline
addi $t1,$zero,0x30
lw $t2,0($t1)
sw $t2,0xff18($zero)
addi $t2,$zero,100
Question is to find hazards existing in the code and the answer is:...
0
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1answer
18 views
Curiosity on system device nomenclature - Gaussian Mixture Models
Would not know if this is the best SE website to ask, but I could not find anything better, especially because the answer might involve a fair amount of computer science (although this is an ...
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0answers
14 views
Associative cache finding the tag and word number
An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes.
I'm unsure how to find ...
0
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1answer
16 views
Is the statement “Control unit controls overall operations of computer.” true or false
I was tutoring a grade 4 student about CPU and I got confused as there are also the other units of a cpu like arithmetic and logic unit and memory unit. So, is the above statement actually true even ...
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0answers
16 views
Number of MUX required for Cache Mapping
I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...
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2answers
24 views
Who decides that process needs cpu time or not?
I wonder how does particular process gets CPU time or resources whenever it's
required to execute some instructions? When a process is in the idle state or waiting for input, it's not occupying the ...
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0answers
5 views
tlb hit/miss after page fault has serviced
when a system gets a tlb miss and the required page is not present in the memory therefore it will trigger a page fault. after the service of the required page fault. will now the request will hit in ...
0
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1answer
14 views
No. of disk blocks writes required for writing the file
Assume that a file is written using write(fd, buf, K) system calls, where fd is the file descriptor, and K, the number of files to be written to the current file offset which is a multiple of the disk ...
0
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1answer
25 views
Is OS mode required for accessing general purpose registers
In which of the following cases a process executing in user model is required to enter into the OS mode?
(a) Decreasing the value of unsigned integer value in a register to less than 0
(b) Accessing ...
2
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1answer
60 views
How do I count the exact number of executed commands for a MIPS program?
I want to know what the best way is to count the number of executed commands for a given MIPS program. Let's say we're given a simple for loop that counts from $0$ to $100$. For this I would write the ...
-1
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0answers
10 views
For a given number of sets, what effect does increasing associativity have on the miss ratio?
2 For a given associativity, what is the effect of increasing the number of sets?
3 For a given cache size, how does the miss ratio change when going from an associativity of one to two to four? ...
0
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0answers
9 views
definition of speedup for Amdahl's law
Say I have an algorithm C running in time T that decomposes into two "subalgorithms" A and B that run in time p*T and (1-p)T so that algorithm C takes time pT+(1-p)*T.
Say I have another algorithm C' ...
0
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0answers
18 views
Register output glitches and memory writes
When changing the write enable signal, of a memory element, from 1 to 0, what effect does the pipeline's register's output glitch have? Glitch that all of digital logic has, for the time of ...
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0answers
25 views
How to find percentage of CPU time consumed during DMA operation?
Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
0
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1answer
27 views
Pipelining and instruction cycle
I was solving some problems on number of clocks required in pipelining. However I came across this problem,
Consider the sequence of machine instruction given below:
MUL R5,R0,R1
DIV R6,R2,R3
ADD R7,...
0
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1answer
33 views
Cache and Main Memory
As we know that average access time is given by
t=p*(tc)+(1-p)*(tc+tm)
where t represent the average time, p is the hit ratio , tc is the time to access the data from the cache and tm is time to ...
0
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0answers
25 views
Handling of $HALT$ instruction
I have been reading $CO$ by Carl Hamacher. I have read generally $PC$ is incremented during the fetching phase of the instruction only, so if interrupt occurs because of branching or call during ...
0
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1answer
47 views
Any CPUs using value prediction, dynamic instruction reuse?
There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
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0answers
4 views
Does VMX Root and VMX Non-root Ring 0 enjoy same hardware privilege? [migrated]
I have found following figure from a paper (Intel SGX Explained).
According to this, VMX Root Ring 0 hypervisor enjoy more privilege than VMX Non-root Ring 0 OS Kernel. My question is: other than VMX-...
0
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2answers
52 views
Are all integers kept in 2's complement form in all microprocessors?
Are all integers kept in 2's complement form in all microprocessors or do microprocessors use 1's complement form and unsigned integer form too?
-1
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0answers
6 views
Control unit signal generation
I have this confusion between what exactly control unit generates.
To be very specific there are two types hardwired and micro-programmed.
according to wiki control unit should generate read, write, ...
0
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0answers
13 views
Number of memory cycles stolen for transferring one word
The storage area of a disk has the innermost diameter of 10 cm and outermost diameter of 20 cm. The maximum storage density of the disk is 1400 bits/cm. The disk rotates at a speed of 4200 RPM. The ...
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0answers
14 views
How does an accumulator with an upper and lower half work?
In the article "The IBM Magnetic Drum Calculator Type 650", originally published in Vol. 1, Issue 1 of Journal of the ACM, the article describes a computer architecture with a single accumulator ...
0
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1answer
30 views
Bytes addressable processor
In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
0
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1answer
79 views
How do things work in the fetch phase of the instruction cycle?
There's something that confuses me, in Computer System Architecture(Morris Mano), Chapter 5, the book uses a simple microprocessor which has the following instruction cycle:
e.g. LDA Operation:
AR&...
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0answers
45 views
What is Address Sequencing?
Whenever I've come across this question whether on the internet or in my class everybody mentions the 4 address sequencing capabilities required in a control memory and the steps of address sequencing:...
0
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1answer
15 views
How to count stores in cache analysis of matrix multiplication
I'm trying to understand cache misses/iter and came across this that I couldn't understand or reason out.
For ijk iteration, my slides say that there are 2 loads and 0 stores.
...
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0answers
26 views
cache coherence: false sharing vs. memory coalescing CPU vs GPU
False sharing is defined on CPU as when atleast two cores write to the same cache line. If the two cores have their own private caches, one will invalidate the other's cache line when they write to ...
1
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1answer
40 views
About hardware multithreading
I'm reading Multithreading (computer architecture) - Wiki, aka hardware threading, and I'm trying to understand the second paragraph:
(p2): Where multiprocessing systems include multiple complete ...
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0answers
10 views
Why is it difficult to differentiate between system and user CPU time?
In the book, Computer Organization and Design, Fifth Edition, by D. Paterson, it is stated that
Differentiating between system and user CPU time is difficult to do
accurately, because it is often ...
1
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1answer
28 views
Why is superscalar processor SISD?
From Wiki - Superscalar processor:
(Line 1): superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a ...
0
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1answer
42 views
What is an instruction bus?
I understand how the control, data and instruction buses form the system bus in von Neumann architecture but in the context of Harvard architecture, my textbook refers to "parallel data and ...
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0answers
7 views
What will happen if the total number of entries of a direct-mapped cache is not a power of 2?
In Computer Organization and Design, it says
Because the index field is used as an address to reference the cache,
and because an n-bit field has $2^n$ values, the total number of
entries in a ...
0
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1answer
25 views
How many words of memory map to the same cache entry?
I am going over some practice questions for the Major field exam and it asks:
A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
1
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1answer
15 views
In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?
In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says
Instruction fetch: The top portion of Figure 4.36 shows the
instruction being read from ...
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0answers
15 views
Can mutex locks be implemented in software without hardware support? [duplicate]
Wikipedia mentions some software solutions
but not sure whether these solutions will work for SMP, preemptive systems or for more than 2 processes.
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votes
1answer
57 views
How many RAM chips of size 256k x 1 bit are required to build 1M Byte memory
$$1MBytes =1024*1024*8$$
$$256k*1bit=256*1024$$
$$1MBytes = \frac{1024*1024*8}{256*1024}=32$$
Now my question is that for converting 1MByte to bit level we need 1024*1024*8 but 256K is not converted ...
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0answers
15 views
Is memory possible without a flip flop circuit?
All the memory circuits I've seen use some form of flip-flop/feedback mechanism to store a value. Is this the only circuit design that can store a value?
1
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1answer
26 views
In which environment we use NFA(Non Deterministic Finite Automata)?
We have two types of Automata. One is NFA and second is DFA. These are little bit different but thing is that in which environment we prefer NFA over the DFA?
5
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1answer
64 views
Do most computational efficiency increases due to increased transistor count in the last 70 years depend on some kind of parallelism?
Modern personal computers as far as I understand have increased in power (measured informally by ability to compute “more demanding programs”) due to two “broad factors”:
decreased transistor size (...
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0answers
8 views
Determining the max frequency of a cycle with flip flops
The following cycle is given and i need to determine what is the max frequency possible for it.
The cycle has 3 positive D-edge Flip Flops and some logic gates.
i calculated the time it takes for ...
