Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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How can I connect a drive to a 16 bit custom intel 8088 system?
I'm embarking on a long-term project, aiming to build a computer based on the Intel 8088 architecture. This venture provides an excellent opportunity to deepen my understanding of computer hardware ...
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What are some good books for vlsi cmos design? Or some good educational software?
I'm a student trying to learn more about CMOS design, I already understand assembly and computer architecture, but VLSI is very interesting and I was wondering if you guys knew some good books/games ...
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Understanding atomic requests/transactions in a snooping coherence protocol
I've been reading the book "A Primer on Memory Consistency and Cache Coherency", and it contains the following paragraph:
The Atomic Requests property states that a coherence request is
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Regarding CPU ILP: what actually consistitutes "the current instruction"?
If a CPU is able to execute multiple instructions in parallel, and fetching/decoding/scheduling instructions happen in batches, and there's multiple execution units, etc. What does the IP register ...
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How do you understand Systolic Arrays?
I'm working on a problem from the Digital Design and Computer Architecture course on Systolic arrays.
The question set up is as follows:
The following diagram is a systolic array that performs the ...
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Is the optical disk drive an input device?
I have read online and seen websites saying the optical disk drive is a storage device. In my opinion, the optical disk drive only writes data to the optical disk so it's not a storage device, am I ...
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How are pointers modeled on bit-based computer models?
Why bit-based computer models?
The perhaps most commonly used computer model is a random access machine that can store natural (or even real) numbers in infinitely many cells indexed by natural ...
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Counting the expected number of CPU cycles for n-number of assembly instructions
I was trying to count the cpu_cycles from an ARM processor 4 core Cortex A78 to be exact) using the PMU registers. Now, at the beginning, I read the cpu cycles counter register, then for test just run ...
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Amdahl's law to determine the overall speed increase using the optimizations
There is an old CPU running a program in which memory operations
currently take 30% of its execution time. Scientists find that adding a cache memory
speeds up 80% of memory operations by a factor of ...
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What is the relation of branch instruction in single core CPU v.s. multicore CPU?
In the Computer organization and design book, there is an exercise in chapter 1 that stated:
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Logical address vs physical address
I have been trying to understand the logical and physical address of some data/instruction the logical address is a address generated by the CPU during a execution cycle.So if I write
this code
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Neural networks as building blocks of a computer
I think I have developed a logic circuit which by using combinational logic and flip flops learns to perform the XNOR logic between 2 bits.It is a kind of state machine. Suppose we built a computer ...
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Understanding the Relationship Between CPU Registers Amounts and Maximum RAM in 32-bit Architectures
To my knowledge,
The number of CPU registers can tell us the maximum RAM we can have. I am only talking about physical memory, no virtual memory or virtualization in my question.
A 32-bit CPU ...
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Sequence counter in a hardwired control unit
I have been studying the structure of a hardwired control unit and at 8:57 of this video
we get a basic block diagram.What does the sequence counter do exactly?
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Why when we use DMA , Read/Write operations on I/O devices are faster?
I am wondering why are read/write operations on I/O devices much faster when we use DMA?I must be that when using DMA we have 1 less clock cycle to access the local buffer of a IO device since it is ...
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Function of data pin(s) in a single RAM chip
Consider a very simple RAM chip that has 20 address pins and 4 data pins. I would like to know the function of the 4 data pins when only 1 data pin is enough.
What do I mean by 1 data pin is enough? ...
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RISC-V execution model
I'm reading a text book on CPU architecture and I have something that confuses me: The text book defines 4 different instruction execution models in CPUs, Stack (where a CPU only has a stack and is ...
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How exactly does stale data appear in temporal buffer in Downfall attack?
I've read Downfall paper. In the university, I've had an introductory course on computer organization and operating systems. We also studied Spectre and Meltdown attacks there. I understood the ...
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Assosciative mapping algorithm
I have been studying the assosciative mapping in a cache.Every line in a cache has a unique address which is made of:the index and the offset bits which give the the cache set and the cache line and ...
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R2000 ALU Design
probably a couple decades too late to ask this question, but does anyone know anything/have detailed documentation about the hardware/design underlying the ALU unit in the early MIPS R2000 CPU?
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Why is the Program counter(PC) 12 bits and not 24 bits in IAS computer system?
Why is the Program counter(PC) 12 bits and not 24 bits in IAS computer system? PC is said to have next - instruction pair and an instruction has 12 bit adress and 20 bit opcode, so if it's a pair it ...
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Could there be a computer or components based on a non-classical logic?
Since circuits and processors are heavily influenced and designed based upon boolean logic, which is itself a subset of propositional logic, could there be different interpretations of hardware or ...
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Requirements to a CPU architecture to actually allow a C compiler to be built for it
I have this rather weird CPU architecture for which currently only an assembler exists. I won't go into too much details about this architecture as it is not publicly available. However, some quirks ...
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SOP Boolean expression of state variable and output of a Moore FSM
Disclaimer: I'm studying for an exam, but I don't have to hand in anything.
I have the state transition diagram of the FSM and its states encoding:
I want to find the sum-of-products (SOP) Boolean ...
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I want to get into Operating Systems, where do I start?
I have been doing web/app development for a few years, primarily involving high-level programming and stuff. However, I am interested in jumping into some low-level stuff and genuinely understanding ...
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I/O Complexity Analysis with Memory Hierarchies
How to go about analysing the I/O complexity when there are multiple levels of memory involved? Looking up I/O complexity analyses returns papers such as this one, which generally assume for ...
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Best method to run an optimizing function millions of times
My goal is to find the local minimums of a smooth multivariate function $f_t(\vec y)$ for multiple values of $t$. I have created an algorithm $foo(t,\vec x)$ which returns the results of Newton's ...
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About registers and IMUL
I do not know if this question makes sense
BUT
AX has two halves al and ah but the higher halves of EAX and RAX are not addressable.
When IMUL instruction is executed e.g. IMUL r/m16 the os uses ax ...
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Page-to-Cache mapping
I have a computer architecture exam tomorrow and my professor gave us some questions for practice. I just need to clear some confusions.
The first question is: "a) In a Direct-Mapped Cache, ...
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Concept of a Stream Device
In class, professor mentions that there are Stream and Storage devices. I mean to ask about Stream devices. I've also heard the terminology character devices.
On a Linux VM, the corresponding terminal ...
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Are there any radical approaches in CPU development?
I have a desktop PC with the CPU Intel I7-12700F with 180 TDP, the CPU fan Zalman CNPS10X extreme, and Windows 11 and my problem is that The CPU cooling causes much noise when simple tasks are being ...
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Learn computer architecture and organisation via an oversimplified machine
I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
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Does exist another models like CARDIAC, LMC and IPC?
I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
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How does non-DMA transfers really work?
I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding:
disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
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How does a CPU jump to a instruction thats no longer in ram?
Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
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Execution of instruction in MIPS on various parts of the clock cycle
I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
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In the next ten years, what modifications to hardware architecture do you anticipate being made to enhance machine learning performance?
How do you believe prominent deep learning ASIC makers such as Nvidia and Google will alter their hardware design over the next decade to meet the exponentially expanding need for extra computing to ...
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How to calculate the size of main memory if the cache is 4-way set associative memory, cache memory size is 256KB and number of tag bits is 8
I'm trying to calculate the main memory size, and the only information given is the size of the cache, which is 256 KB, and the number of tag bits, which is 8. Cache is a 4-way set associative memory.
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How is the memory address structured when the number of blocks per cache set is not a power of 2?
When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization:
$$Address = TAG|...
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Why does a 32 bit address only contain 1 byte, when 32 bits = 4 bytes?
I am really confused about it. I think 32 bits = 4 bytes but 32 bit address is only 1 bit.
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Why does the branch instruction stall at fetch?
Here is a problem (C.1.c) from the famous Hennessey & Patterson book
I'm struggling with. The following code fragment should be scheduled
on a five-stage MIPS CPU with "full forwarding and ...
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How a computer works?
I know that a computer can be mechanical, screws/nuts or even water/pipes. Of course, it would be slow and big, but it doesn't have to be electric, transistors, etc. How can a machine like this do all ...
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Within the set of signed integers representable by a bit string of length n, are any two elements equivalent to each other mod 2^n?
Donald Knuth's The Art of Computer Programming, Volume 1 Fascicle 1 contains the following exercise:
If $\alpha$ is any string of 0s and 1s, let $\operatorname{s}(\alpha)$ and $\operatorname{u}(\...
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How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?
In my OS course, the instructor mentioned the following: In UNIX if a parent process creates a new child ("fork") then the child is an exact duplicate of the parent. This means its memory ...
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How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
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CPU limit for bitap algorithm bitmask
We have bitap (shift OR) algorithm that searches for a substring in a text.
Bitap algorithm uses bit masks, so that it can perform bitwise operations very fast with the help of CPU.
For example:
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Is this how endianess work relative to memory?
So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things.
Here is how I look at ...
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Is the reason for a stack to decrease the size of a program (by adding the use of subroutines)?
The stack allows subroutines to be used. It can store return address for "return from subroutine" instruction (RTN) and also arguments for the function.
It is not possible to store return ...
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Help with a question on write-through and no-write allocate in caches
I am struggling with this question as I am not sure whether the answer that has been provided is correct or not. The image should be sufficient to tell the question.
The attached image is of the ...
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What is my mistake in applying the division algorithm using subtract and shift?
The following division hardware is from computer organization and design RISC-V 2nd edition 2020, section 3.4.
Using this hardware and its related algorithm, I want to calculate 43 / 2. I use 6 bit ...
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