Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
995
questions
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Inquiry about the power usage of my pc [closed]
I use a pc having an asus monitor and a very old cpu. I just wanted to know how much electricity will my pc consume if I am just reading a pdf on it or browsing something. I have an asus monitor(17 ...
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2answers
163 views
What kind of binary compatibility is present for 2 processors sharing an Instruction Set?
Consider Intel x86 and AMD x86 Processors. As I understand, since they use the same Instruction Set, in theory an application compiled for Intel x86 processor would run without any modification on ...
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14 views
Bus Bandwidth Calculations
I cannot understand this question and the model answer for it and I wonder if anyone here is able to help me.
Question:
...
0
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2answers
33 views
In what stage is next PC address available or known to the processor?
Assuming you know the meaning of pipelining in Computer architecture & organization. When is the next PC address or jump address available or known to the processor?
In this lecture, https://youtu....
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1answer
25 views
Memory Address Lines
I am reading a text book by David Tarnoff and there is something I do not understand, the section is on CPU and memory. The book states that the number of address lines going into a memory device ...
4
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2answers
195 views
Why did finite-state controller with datapath win?
I just finished watching the 1986 SICP lectures, and the concepts are rolling around in my head.
My question: why is "finite-state controller with datapath" the implementation of computer ...
0
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1answer
22 views
What would happen if while making a connection between memory and CPU, the address lines get's interchanged
While making a circuit connection between Micro Processor and Memory Chips, the Address Lines A0 and A1 got interchanged. Means A0 of address bus got connected wrongly with A1 of Memory chip and A1 of ...
2
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1answer
35 views
How does software prefetching work with in order processors?
From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching:
...
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0answers
22 views
logic and communication technicalities between computer components
Concerning modern computers communicating with each other it is my understanding that computers are reading patterns in current flow and interpreting those patterns of current flow as ours 1's and 0's....
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3answers
99 views
Cache coherence is worthless and does nothing?
When you perform a write on a multi-cpu system, relevant cache flushes are done to ensure that the other cpus see the change immediately.
BUT
That write was issued from an independent thread on a ...
5
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1answer
54 views
Understanding IBM370 Relaxed Memory Consistency
In the report "Shared Memory Consistency Models: A Tutorial" (https://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf), the authors explain the difference between IBM370, Total Store ...
0
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1answer
20 views
Average Access time in caches
I know that the average access time for systems with level 1 caches is:
Average Access Time = Hit time + (Miss Rate x Miss Penalty)
How can this be generalized for n level caches?
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1answer
48 views
Assembly Language Step By Step: Why deviate from the norm and design computers where the presence of voltage encodes a 0 bit?
That the presence of voltage across a switch encodes 12 is purely arbitrary... Jeff Duntemann's book mentions:
We could as well have said that the lack of voltage indicates a binary
1 and vice versa (...
2
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1answer
49 views
Why does CLRS refer to the disk parts as pages rather than blocks?
I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters:
In order to ...
0
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0answers
30 views
How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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0answers
25 views
What is the maximum memory address space that microprocessor can access directly if a 16-bit memory module is interfaced with a 32-bit microprocessor?
The Complete question is as follows :
Consider a single-address 32-bit microprocessor with 32-bit address bus and 32-bit data bus. Its
instructions composed of 1-byte opcode and 3-byte operand address....
1
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1answer
33 views
What is a forwarded clock?
I'm reading the overview book of the Intel QuickPath Interconnect and it says there:
The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a ...
0
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0answers
27 views
Identifying problem in MIPS pipeline datapath
I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
1
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1answer
46 views
How to determine the bits of the address used to access the cache?
Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a ...
2
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2answers
55 views
Interrupt enabling and disabling
While reading about interrupt mechanism, I understood that there is an IRQ signal line on the bus by which an I/O interface
raise an interrupt request.
There is an INTA signal line using which the ...
0
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0answers
7 views
Finding Worst and Best Case Hit Rate of a Cache Given Code
I'm doing some practice problems to study and came across this one:
Consider a 8-way set associative cache with 64 B blocks, and 64 total blocks as part ofa 16 bit physical address.
Imagine we use the ...
0
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2answers
42 views
Why is programmed I/O not suitable for high-speed data transfer?
I am learning about computer architecture and organization.
I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
0
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1answer
21 views
Can synchronous data transfer be used for transferring large data in case of computer architecture and organization?
I am learning computer architecture and organization.
I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization?
I ...
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0answers
25 views
Transactional memory
I would like to understand what role does Transactional memory plays in memory organization, I know that To allow for more efficient parallel programming with higher performance, processor implements ...
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0answers
26 views
How does virtual and physical memory affect cache structure?
Working with a question that states:
Consider a hypothetical machine in which physical address space is
of 512 words and virtual address space is of 2048 words. The page
size is 8 words. What is ...
2
votes
3answers
70 views
Speed of a microprocessor
I was just wondering why are are new generation microprocessors faster at the same clock speed as the old ones.
For instance a 2.66Ghz dual core i5 is faster than the a device with clock speed of 2....
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1answer
52 views
Manipulating stack pointer in assembly
I have written an assembly program to store digits in a stack. And to print the digits I have used
loop2:
mov ah,2
int 21h
sub cl,1
jnz loop2
But this would only ...
0
votes
1answer
18 views
Dividing EX stage of a pipeline into EX1 and EX2 stages
There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be:
In the five stage pipeline with forwarding support to EX, the first operand of ALU ...
0
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0answers
21 views
Cache consistency in uniprocessor system
In a uniprocessor system, can we have a Cache consistency problem? For sure, it exists in a multiprocessor system. But I wonder if it exists in a uniprocessor system and in which scenario.
1
vote
1answer
19 views
Throughput increase/decrease by how much percent
I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me?
The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
0
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0answers
203 views
Difference between multiprocessor and uniprocessor in terms of run-time system
In the book "Advanced computer architecture and parallel processing" (El-Rewini & Abd-El-Barr), there is a question in the exercises of chapter 1 that needs the reader to compare between ...
0
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1answer
41 views
how does the program change the clock speed of the processor?
bios is a program that checks all devices and starts the bootloader.
but how does the CPU sync with the motherboard if the CPU clock settings are stored in the BIOS?
Does the BIOS have CPU clock ...
12
votes
2answers
3k views
How is conditional jump implemented in the CPU?
After reading the question I'm still not sure how CPU does branching.
I understand that we have an instruction counter which points to the current instruction. And after performing conditional jump it ...
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vote
3answers
36 views
Negative Numbers in 32 bit Floating Point IEEE Numbers
So I understand the logic behind converting positive decimal numbers to IEEE 32 bit floating numbers but I'm not completely sure behind the negative one's. If for example we have a decimal number say -...
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0answers
80 views
What do “JAMZ”, “JAMN”, and “JMPC” stand for in Mic-1?
I am wondering what do JMPZ, JMPN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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vote
2answers
32 views
Adding two numbers in base 2(floating point) vs Multiplying two numbers in base 2(floating point)
Is it true that adding two numbers in base 2 is more complex than multiplying them? If so can someone please explain why this is the case?
0
votes
1answer
31 views
When the stall is actually going to happen?
Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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vote
0answers
43 views
Can old hardware be practically useful for CS problems of modern day?
Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
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0answers
18 views
How many cycles required in Instruction Level Parallelism?
L1: LD F1,0(R2)
L2: LD F2,8(R2)
L3: FADD F3,F1,F2
L4: SD F3,8(R2)
If the instruction fetch for L1 starts at clock cycle 1, in which cycle the instruction L4 access memory to store the data?
I am ...
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0answers
21 views
What percentage should be parallelized?
While exploring about the 2-core system. The voltage decreases linearly with the frequency. The voltage may not decrease below 75% below the original voltage.This voltage is referred to as the voltage ...
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votes
3answers
127 views
Can x86 Instruction Set be changed with microcode update?
How I understand microcode translate an instruction to microinstructions. And CPU has a unit that stores all possible of microinstructions. These microinstructions can be changed, because it load ...
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1answer
39 views
How does a computer direct the processing of information
So I'm reading Introduction to computing systems:From bits and gates to C and beyond, and the author states that a CPU is the mechanism that
...directs the processing of information. Which is ...
2
votes
1answer
64 views
Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?
A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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1answer
61 views
What is combinational circuit?
I'm reading the Digital Design and Computer Architecture by David Harris, Sarah Harris. The authors give the following definition of combinational logic:
A combinational circuit’s outputs depend only ...
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0answers
9 views
Power8 addressing modes
I want to understand what are addressing modes that can be used in IBM Power8 microprocessors.
In Pdp 11, Most operands can apply any of eight addressing modes to eight registers.
But how having 124 ×...
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vote
1answer
46 views
How do I compute the power consumption of a DRAM refresh?
Given a DRAM-based memory system with a total capacity of $x$ bytes, $y$ DRAM rows and a refresh time of $t$ milliseconds, how do I compute the power consumption for one DRAM refresh? I couldn't find ...
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0answers
40 views
Can a single core processor be MIMD?
I was wondering for if a single core processor can be MIMD? or MISD? or SIMD?
I thought MIMD's requirement is multicore, but I am not sure about this
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0answers
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Min number of register without spilling
The program below uses six temporary variables a, b, c, d, e, f.
a = 1
b = 10
c = 20
d = a+b
e = c+d
f = c+e
b = c+e
e = b+f
d = 5+e
return d+f
Assuming that all ...
0
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1answer
41 views
When can a deterministic finite-state-automaton (DFSA) along with its input sequence be said to be a part of another DFSA?
For a Finite State Automaton / Finite State Machine (FSM) $F$, that has an input alphabet, a set of possible states, an initial state, a set of possible final states and a state transition function, ...
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1answer
55 views
Interesting Speedup & Amdahl's law problem
I have found a problem on my Computer Architecture textbook which I have some issues with:
We have a process which spends its time in the following way:
50% of the time, it executes common ...
