Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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Cache mapping calculation
A cache has following specifications:
Block size = 16 Bytes
Set size = 2 way set associative
Number of sets = 128
Physical address = 23 bits, byte addressable
My Questions are:
1) How many blocks ...
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AMAT using Local miss rate, global miss rate, local hit rate, global hit rate
Consider the following scenario as shown in image:
I have summarized the above Memory layout in terms of Miss rates and hit rates:
...
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1answer
62 views
Can a CPU be replaced without interrupting the processes running on it?
When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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Need help understanding set-associative cache
The problem I'm trying to solve is:
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main ...
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Does the Hack computer from “The Elements of Computing Systems” use Von Neumann architecture?
I'm reading "The Elements of Computing Systems" (subtitled "Building a Modern Computer from First Principles - Nand to Tetris Companion) by Noam Nisan and Shimon Schocken.
Chapter 4 is about machine ...
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Regarding Amdahl's balanced system law
One of the paper titled "Rules of Thumb in Data Engineering" (Jim Gray et. el.) mentions some calculations based on Amdahl's balanced system law.
Link to paper: https://www.microsoft.com/en-us/...
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2answers
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Why is there no extensive Standards Body overseeing ISAs, Bitcodes, Code Representation, etc… as there is in the case of Unicode
There exist a vast array of prominent bitcode formats, each suited for their specific task:
LLVM IR:
This format is build around a XML like binary streams model, designed to be used as a common ...
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1answer
89 views
Create NOT gate from other gates
If we are given only one NOT gate and any number of OR and AND gates, then, can we simulate more NOT gates?
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25 views
Is the control bus “measured” in the number of bits it have?
In the system bus, the data bus and the address bus are "measured" in the number of bits that they have, for example we may say that the data bus is 32-bit and the address bus is 32-bit for some CPU ...
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1answer
66 views
Does RAM take the copy of the program or does it load programs from the hard disk?
I guess it copies, since it is a temporary memory, it will erase if power is not supplied, so, that will lead to data loss right, but still, I need clarification.
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5answers
81 views
Which memory holds the copy of the program that is to be executed?
I don't know whether it is RAM or cache; I can say that isn't the registers since their memory capacity is very small.
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1answer
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Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?
I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
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1answer
37 views
Slowdown when accessing data at page boundaries?
Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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In Tomasulo's algorithm, how do reservation stations recognise which results are directed to them, especially where functional units are pipelined?
I am currently researching instruction level parallelism in CPUs and have come across Tomasulo's algorithm for dynamic scheduling.
As I understand it so far, once a functional unit computes a result,...
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2answers
44 views
How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?
I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together.
If, for example, instructions are meant to be fetched in one stage of ...
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2answers
41 views
Confusion in speed up calculation for pipeline architecture
This is an online question I am trying to solve.
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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1answer
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If the Intel Pentium processors, was not made compatible to programs written for its predecessor, it could have been designed to be a faster processor
I find this question while solving some government job question bank. If someone could provide the answer along with a little explanation it would be very helpful.
Ques:- If the Intel Pentium ...
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cache Hit rate and miss rate calculation one-way associative
I have this problem:
A program that calculates the sum of 128x128 matrix of 32-bit integers (by rows). I have one-way cache that has 8 sets with block size of 64 bytes, considering only the access to ...
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3answers
94 views
How is an Assembly Language Processed by a CPU's Circuitry?
I'd like to have a bit more understanding of how, on a circuitry/hardware level, an assembler program works.
I think I have a very broad-brush understanding of how a CPU would process machine code on ...
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1answer
26 views
Compute cache miss rate for the given code
Problem Description:
We consider a 128-byte data cache that is 2-way associative ($E=2$) and can hold 4 doubles in every cache line. A double is assumed to require 8 bytes.
For the below code we ...
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1answer
28 views
Calculate Stages in Non-Pipelined Processor
I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :-
...
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0answers
19 views
Problem regarding caching. Block offset, Set index and Tag
I am currently reviewing for my exam in computer architecture. I've run into a question in the old exam sets that I can't really figure out. The question is regarding caches, more specifically block ...
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State-machine semantics of instruction set architectures
An instruction set architecture is an abstraction, a common interface layer between the software and the micro-architecture. The existence of this clearly delineated interface is becoming increasingly ...
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1answer
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Doubt on Floating Point Representation [closed]
$1-2^{-23}$ and $2-2^{-22}$ both represents floating point representation or normalised representation.But are those two represent same value or both have different value? Is floating point ...
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How to determine index being access in memory
Having 4GB byte addressable main memory in 32-bit system divided into block of size 1024 bytes.
If processor wants to access a memory location 0xFC347004. Corresponding block is found in cache.
...
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2answers
51 views
In what sense are dataflow architectures non-deterministic?
The Wikipedia article mentions non-determinism in the context of dataflow architectures. Arthur Veen's paper mentions non-determinism when it elaborates on MERGE nodes as conditional constructs.
Are ...
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1answer
14 views
Case where anti-dependency doesn't need pipeline stalling
While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling.
But i couldnt find at example for ...
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What is tag-only forced cache inclusion called?
Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data?
Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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1answer
171 views
What uses have been proposed for overlaid skewed associativity?
In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
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49 views
What is this weird gate?
This came from a picture of something that I'm supposed to make, and I can't find it in the program I'm supposed to use (LogicWorks). It looks like it 'not's only one of its inputs, but that doesn't ...
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1answer
36 views
Problem Set Solutions/Interrupts & Exceptions/Problem 1
Using Tomasulo’s algorithm, for each instruction in the listed sequence determine when (in which cycle, counting from the start) it issues, begins execution, and writes its result to the CDB. Assume ...
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1answer
25 views
What architectural features will allow this microprocessor to access a separate “I/O space”?
I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition):
Consider a hypothetical microprocessor generating a 16-bit address
(e.g., ...
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2answers
113 views
Why do we still use a Von Neumann Architecture in modern computers?
The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons.
To this day the Von Neumann ...
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3answers
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Program counter in a CPU
I know that the CPU has a program counter which takes instructions that are required to execute a program, from the memory, one by one. I also know that once the first instruction is executed, the ...
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How do I solve the part (a), of the following question?
The problem I'm facing is how do I know whether the mapping is "1-way set associative", "2-way set associative", "4- way set associative", etc.
Please help!
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2answers
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Address bus and memory
If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it?
What I'm trying to ask is that do all the 65536 locations ...
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Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
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1answer
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Address and data bus
When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about?
Also, why is the address bus unidirectional, as opposed to the data bus?
...
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1answer
63 views
Finding $t$, $r$ and $w$ in Cache - Direct Mapping
I had a question in my past System Architecture exam and I am not sure how to solve it.
Question was this:
Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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76 views
Total bits required for a direct-mapped cache
I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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3answers
121 views
Difference between RAM and buffer
I have searched but didn't get any exact difference between RAM and a buffer. If both are used for temporary storage, then why they are named differently while both having same property?
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Timing of Synchronous/Asynchronous Bus Operation
What is difference between Synchronous and Asynchronous Bus Operations. And how are they change in read cycle and write cycle ??
I shared a website it tells these bus operations bu I didint understand ...
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3answers
77 views
Connection between CPU address bus and max amount of RAM
So, i'm stack on the following question > "A system has a 12 bit address bus. What is the maximum amount of RAM that can be installed on the system?"
First of all, is this question correct? If so, ...
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1answer
40 views
Is Carry Look-Ahead adder used in modern ALUs?
I recently came across carry look-ahead adder(CLA) in David and Sarah Harris's book(Digital Design and Computer Architecture). The circuitry for a 64 bit number (standard integer size in C) is ...
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1answer
86 views
Reasons for choosing register number and address sizes in an Instruction Set
Why would it be suitable to design an instruction set with 2-bits allocated for the register number and 10-bits allocated for the memory address? Would introducing a cache change this? (If possible I'...
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Why does Skillicorn's Taxonomy allow us to design 30 models?
In Skillcorn, David B, "A Taxonomy for Computer Architectures", IEEE Computer, 21(11):46-57, Nov 1988, a taxonomy of multiprocessor architectures is described.
My teacher said that Skillikorn's ...
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2answers
560 views
What is von Neumann bottleneck?
According to this Quora post,
It refers to two things: A systems bottleneck, in that the bandwidth
between Central Processing Units and Random-Access Memory is much
lower than the speed at ...
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3answers
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Does increasing k in a k-way set-associative cache always lead to a better miss rate?
As far as I know a 2-way set-associative cache works better than a one-way one considerably but going to 4 and 8-way caches leads to a marginal improvement. My question is: does increasing K (going ...
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110 views
CRC computation speed vs polynomials features
I tried to find information about how features of a CRC polynomials influence computation speed of implementations.
It is obvious that (depending from the CPU architecture the algorithm runs on) ...
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How does computer work? [duplicate]
I am not a computer scientist or even a student of CS. I just want to find more information and would like if someone could put if in right direction about how actually computer works. I understand ...
