Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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New computer advertises 'No HDD' [closed]
It is my understanding that 'No HDD' mean 'no hard drive detected'. Why would Hewlett-Packard advertise that as a feature on a new HP All-in-One computer that I am considering purchasing? Isn't that ...
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I/O Complexity Analysis with Memory Hierarchies
How to go about analysing the I/O complexity when there are multiple levels of memory involved? Looking up I/O complexity analyses returns papers such as this one, which generally assume for ...
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Best method to run an optimizing function millions of times
My goal is to find the local minimums of a smooth multivariate function $f_t(\vec y)$ for multiple values of $t$. I have created an algorithm $foo(t,\vec x)$ which returns the results of Newton's ...
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CPU interrupt load
I'm currently taking MIT 6.004 course. In one of the chapter regarding interrupts it says:
"There are several calculations we need to do when thinking about recurring interrupts.
The first is to ...
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About registers and IMUL
I do not know if this question makes sense
BUT
AX has two halves al and ah but the higher halves of EAX and RAX are not addressable.
When IMUL instruction is executed e.g. IMUL r/m16 the os uses ax ...
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Page-to-Cache mapping
I have a computer architecture exam tomorrow and my professor gave us some questions for practice. I just need to clear some confusions.
The first question is: "a) In a Direct-Mapped Cache, ...
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Concept of a Stream Device
In class, professor mentions that there are Stream and Storage devices. I mean to ask about Stream devices. I've also heard the terminology character devices.
On a Linux VM, the corresponding terminal ...
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Are there any radical approaches in CPU development?
I have a desktop PC with the CPU Intel I7-12700F with 180 TDP, the CPU fan Zalman CNPS10X extreme, and Windows 11 and my problem is that The CPU cooling causes much noise when simple tasks are being ...
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Learn computer architecture and organisation via an oversimplified machine
I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
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Does exist another models like CARDIAC, LMC and IPC?
I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
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How does non-DMA transfers really work?
I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding:
disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
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How does a CPU jump to a instruction thats no longer in ram?
Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
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Execution of instruction in MIPS on various parts of the clock cycle
I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
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In the next ten years, what modifications to hardware architecture do you anticipate being made to enhance machine learning performance?
How do you believe prominent deep learning ASIC makers such as Nvidia and Google will alter their hardware design over the next decade to meet the exponentially expanding need for extra computing to ...
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How to calculate the size of main memory if the cache is 4-way set associative memory, cache memory size is 256KB and number of tag bits is 8
I'm trying to calculate the main memory size, and the only information given is the size of the cache, which is 256 KB, and the number of tag bits, which is 8. Cache is a 4-way set associative memory.
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How is the memory address structured when the number of blocks per cache set is not a power of 2?
When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization:
$$Address = TAG|...
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Why does a 32 bit address only contain 1 byte, when 32 bits = 4 bytes?
I am really confused about it. I think 32 bits = 4 bytes but 32 bit address is only 1 bit.
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Why does the branch instruction stall at fetch?
Here is a problem (C.1.c) from the famous Hennessey & Patterson book
I'm struggling with. The following code fragment should be scheduled
on a five-stage MIPS CPU with "full forwarding and ...
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How a computer works?
I know that a computer can be mechanical, screws/nuts or even water/pipes. Of course, it would be slow and big, but it doesn't have to be electric, transistors, etc. How can a machine like this do all ...
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Within the set of signed integers representable by a bit string of length n, are any two elements equivalent to each other mod 2^n?
Donald Knuth's The Art of Computer Programming, Volume 1 Fascicle 1 contains the following exercise:
If $\alpha$ is any string of 0s and 1s, let $\operatorname{s}(\alpha)$ and $\operatorname{u}(\...
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How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?
In my OS course, the instructor mentioned the following: In UNIX if a parent process creates a new child ("fork") then the child is an exact duplicate of the parent. This means its memory ...
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How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
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CPU limit for bitap algorithm bitmask
We have bitap (shift OR) algorithm that searches for a substring in a text.
Bitap algorithm uses bit masks, so that it can perform bitwise operations very fast with the help of CPU.
For example:
...
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Is this how endianess work relative to memory?
So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things.
Here is how I look at ...
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Is the reason for a stack to decrease the size of a program (by adding the use of subroutines)?
The stack allows subroutines to be used. It can store return address for "return from subroutine" instruction (RTN) and also arguments for the function.
It is not possible to store return ...
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Help with a question on write-through and no-write allocate in caches
I am struggling with this question as I am not sure whether the answer that has been provided is correct or not. The image should be sufficient to tell the question.
The attached image is of the ...
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What is my mistake in applying the division algorithm using subtract and shift?
The following division hardware is from computer organization and design RISC-V 2nd edition 2020, section 3.4.
Using this hardware and its related algorithm, I want to calculate 43 / 2. I use 6 bit ...
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To where is the mouse sending signals of a computer?
When we move the mouse, we can see the cursor moving on the monitor. I know that mouse can send signals according to its movements. Which component of a computer is receiving those signals in the ...
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Von Neumann Architeture
Recently I came across with a question about Von Newman architecture (which is usually used) and whether the following statement is true or not?
In Von Neumann architecture data are stored in disk and ...
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Perform subtraction micro operation R3←R1-R2 where R1=1011 and R2=1100
From tutorials point:
Subtract micro-operation are using minus operator we create 1's complement and add 1 to the register which obtains subtracted, i.e R1 - R2 is similar to R3 → R1 + R2' + 1
$$
R2'...
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How many bits are needed to reference physical vs virtual addresses?
I trying to learn about virtual memory at the moment and one of the explanations I've look at has a diagram like below. You can see that 32 bit virtual addresses are used so the virtual address space ...
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K-Maps (Digital Logic, Computer System Architecture)
While i was going thru my course in Computer System Architecture (book taken Morris Mano) , I saw a question on KMaps can be solved in either of the ways but couldn't get which one to use when :-
I’m ...
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Are variables stored again in RAM?
Assuming this set of instructions:
declare variable 'A' which has value 5
declare variable 'B' which has value 2
From what I've understood, those instructions are loaded into RAM an then read by CPU,...
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Why is static recompilation not possible?
I'm researching static recompilation but there doesn't seem to be too much information about the subject. I've heard that dynamic recompilation (emulation) can be up to 6 times slower than native ...
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What is the most critical component of a processor? [closed]
We know that there are basically 3 fundamental parts of a processor namely :
Control Unit (CU)
Arithmetical Logic Unit (ALU)
Clock
Also we know that they maintain several important and different ...
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Tomasulo's Algorithm: Is there one reservation station per functional unit?
In Tomasulo's algorithm, is there only one reservation station per functional unit (even with multiple same-function FUs like, say, 3 adders)? Can there be more?
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Page/Frame VS Block
I am bit confused on these terminologies.
While studying Paging of Operating System we study about Page and Frame.
Size of one Frame of Main Memory = Size of one Page of a Process
While studying ...
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Is the memory layout actual or virtual?
In many computer architecture books (e.g. Computer Organization and Design), the memory layout that is seen by a program is as the following figure.
But I wonder about multitask computers, in which ...
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If a process needs more RAM, does the Page size simply get bigger or does it get a new page?
Let's say I have a Operating System with 4KB page size, but I need to allocate 8kb of memory for all the variables. Does the Process get new page (second one) or does the current page table simply get ...
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What happens in harvard architecture pipelining if cpu needs to write data and fetch data at the same time?
What happens if Operand Fetch and Write Back happen in same cycle?
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Formal proof for in-balanced pipeline throughput
It is a well known fact, the throughput of a given compute pipeline (say, CPU instruction pipeline) is determined by its "slow" segment.
All the resources I've seen so far, demonstrates this ...
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Risc v Instruction format
Why do you think the Immediate type instructions are limiting its immediate values to only 12 bits, while upper immediate type instructions can handle immediate values of 20 bits.
user154360
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Understanding the faster multiplication hardware in riscv
I found a one question I wonder, but there is something to be clear about.
The link is https://electronics.stackexchange.com/questions/56488/parallel-multiplication-hardware/56518#56518
Q1. In his ...
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What is a procedure?
Non-computer scientist here, trying to understand what SICP (Structure and Interpretation of Computer Programs) means by a procedure, whether it matches the dictionary definition, and also how a ...
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How does instruction set architecture affects clock rate?
According to the computer organization and design RISC-V 2nd edition 2020, section 1.5, the following table states that ISA affects clock rate.
Hardware or software component
Affects what?
How?
...
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Solving an ambiguity concerning unsigned and signed integers [duplicate]
I am taking a class in computer science and I am not sure about the following. When one transforms $247_{10}$ into its binary counterpart one gets $11110111_2$. However, the same binary number ...
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translating operations per second (OPS) to floating point operations per second (FLOPS)
I have some algorithmic complexity estimates in Giga Operations Per Second (GOPS) and I would like to compare those with the capabilities of state-of-the-art processors. However, the processor ...
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Is assembly macros part of operative system / kernel, or lower down and more seen as hardware?
Update: To clarify. MyNOR (http://mynor.org/) stores some combined instructions in ROM to make programs take up less space. It seems very possible that instruction sets for CPUs might do similar, in ...
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How hardware write a byte in memory?
I want to know how hardwares write a byte in memory?
If there is difference between writing process in RAM and ROM I would like to know as well.
Specially I want to know:
Is hardware writes values ...
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Why do computers become slow over time (HW PoV)?
I'm a SW engineer. I'm just curious why computers become slow over time.
"Slow" here I mean from a usual user PoV:
It takes more time to launch an application.
Application UI takes longer ...
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