Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How do computers *really* work? (at the most basic level)

While learning about computers I will read about RAM and Storage and the CPU, and while these explain the architecture of a computer and how parts of a computer work together, I still don't understand ...
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About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor. We do assume that ...
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26 views

What will a given CPU architecture do in the event that we were to invert all of the instruction bits to a given instruction?

Given an arbitrary CPU - Architecture and its instruction set... What would be the outcome of the given inverted instruction within that Architect? For simplicity, let's use an 8-bit CPU architecture ...
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421 views

Representation of unsigned integer on a little endian, big endian computer

This is a GATE 2021 exam question. If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices ...
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K-Map Reduction Grouping Question

I have a simple question regarding reduction using K-Maps. My professor gave this example: While I somewhat understand that we can only group quantities of base 2 numbers, why did my professor group ...
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How to do -8 x -8 in a 4 bit booth multiplier?

In the general case of an n bit booth multiplier, the maximum negative value is -2n-1. So with 4 bits we can represent -8 x -8 (M=1000, Q=1000). Now if we follow Booth's algorithm for multiplying n-...
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Which has optimum performance? raw core or multithreaded

Let's say there's a single process performed in the machine which utilizes all available processors (whether physical or logical processors). The process use 100% processor utilization most of the ...
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How does Instruction Set Architecture (ISA) affect performance?

If 2 CPUs have the same Instruction Set Architecture, which of the following properties will be the same? Clock Rate CPI Execution time No. of instructions MIPS
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How was von Neumann's architecture turned into a parallel capable architecture and is there any limitations to that?

Back when von Neumann came up with his computer architecture parallel machines and multi-core processors weren't a thing but now almost all machines have multiple cores and are able to run programs in ...
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Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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How do I compute the address of the next element?

I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
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106 views

Metrics on which Clock Cycles Per Instruction(CPI) depends

In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this: The term clock cycles per instruction, which is ...
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81 views

Must a Turing machine tape be binary?

I once asked why does computer data bits are usually organized on binary (base 2) sets, rather than on unary (base 1) sets, aiming to also understand why its not also ternary (base 3), heptary (base 7)...
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Minimal number of resources such that the system is considered safe?

In a system with a single type of resource, there are 8 processes with the following maximal requirements: Process P1 P2 P3 P4 P5 P6 P7 P8 MAX 75 60 65 35 30 45 30 30 Specify the minimal value for ...
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Why do register machines outperform stack machines?

Wikipedia says stack machine “designs have though been routinely outperformed by the traditional register machine systems, and have remained a niche player in the market.” Why is this?
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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How Can We Classify Summit Supercomputer in Terms Of Topology

Summit supercomputer has Processor: IBM POWER9 22C 3.07GHz Interconnect: Dual-rail Mellanox EDR Infiniband. So how can we classify in terms of topology? How can I find resources about this subject?
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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46 views

What is the difference between speculative execution & branch prediction?

In computer architecture I'm confused between speculative execution & branch prediction. Are the same or different?
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What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
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55 views

How are programs split up into pages in Memory Paging?

I am a bit confused about how the logical addresses are generated in a paging memory architecture and where and when a program is split up into pages. I understand how logical addresses are translated ...
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51 views

Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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22 views

Were boolean logic used in the analog computers?

I began a simple collection of the events behind todays computers. My knowledege in these fields is so limited, and I read: "In the 1930s and working independently, American electronic engineer ...
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Computer Architecture, Memory Interleaving. Decoding step can be interleaved?

A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ ...
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1answer
45 views

What is the theoretical minimum number of “switches” requried to implement a Turing-complete CPU?

Where "switches" are the basic abstract building blocks for logic gates: vacuum tubes, transistors, magnetic relays, or whatever. We're not counting any switches in the RAM or tape drive ...
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68 views

What is a cache write miss?

I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393; The other key ...
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Double Write After Write Dependency in out-of-order/in-order executions

What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register. We know we can solve a simple WAW dependency by ...
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Cache Direct Map access confusion

Ok, I've found a good example But it doesn't really answer my question. Simple Example We have a 8 two-word blocks. So we have an offset of 1 bit. Say we have two references 33 and 32. ...
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24 views

how to calculate the speed of memory

I checked my Mac, it shows the memory is 16 GB 2400 Mhz, does it mean that the bandwidth is $ \dfrac{16\times1024}{8} \times 2400$, is there any thing wrong with that calculation, because the value ...
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1answer
50 views

Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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14 views

Do industrial automation PLCs have their own special purpose firmware or Instruction Set Architecture?

What is the ISA on the top of which the Programmable Logic Controllers run? Do they have one like in our personal computing devices having Intel x86, amd64 or ARM architecture for smartphones?
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Memory Invalidation and Misses

Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's ...
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1answer
56 views

Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?

Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years. Or the frequent changing of smartphones has a ...
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How would I go about calculating the index field / tag field?

For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas? Given a cache that holds 512 words and block size of one word. ...
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132 views

How would I calculate the cache hit rate (ratio) percentage?

If I am correct the hit rate formula is: Hit ratio = successful hits / total requests... so would the question below be formatted as such: I tried 4 entries / 8 memory accesses but that wasn't right ...
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How to compute the Cycles in a pipelined single cycle processor

I'm an undergrad studying computer engineering and I'm in my first of many courses on computer organization/architecture. In the lectures and online I see diagrams like the one pictured below from the ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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2answers
66 views

Harvard processor structure

In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
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45 views

Why did Apple include dedicated a neural network “processor” in standard consumer products?

Not sure if this is the right place, but I guess it is better than Reddit and I couldn't find any discussion. I was wondering why Apple include a neural network "processor" and can't help ...
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Help understanding main memory to cache block mapping

I'm currently self-learning on the cache memory and have come across a method on how to find out which cache block a memory address will be mapped to: ...
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1answer
69 views

Definitions of Computer Architecture and Computer Organization seems confusing

So there was this question in one of my class tests. It may seem very simple and straight-forward, but I am unable to catch up with its meaning or explanation. I have referred my textbook of COMPUTER ...
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20 views

Why return address may be lost and information in mask, processor registers may be ambiguous if an interrupt is acknowledged in following situation?

In the text Computer System Architecture (3rd Edition) by M Morris Mano , on pg. 415 under the section parallel priority interrupts I came across the following statements. The bit in the interrupt ...
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What does “associative” exactly mean in “n-way set-associative cache”?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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Calculating the pipeline speed up in case we have an infinite amount of stages

I have the following question: We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of ...
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25 views

Hardware implementation of direct mapped , set associative mapped and fully associative cache

I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
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If an instruction contains an address, how is it copied to the MAR?

Since the Memory address bus is unidirectional, how is an address copied to the MAR if a previous instruction such as "STO 150" contains an address? STO would store the contents of the ...
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124 views

Is there code below microcode?

Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
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Types of recordings on magnetic disks

Is my searching about the types correct? Types of recordings on magnetic disks Write: The current which goes through the coil produces magnetic field and then the pulses are sent to the head which ...
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19 views

Reference asking : High Performance Computer Architecture

Topics Pipelining: Basic concepts, instruction and arithmetic pipeline, data hazards, control hazards, and structural hazards, techniques for handling hazards. Exception handling. Pipeline ...

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