Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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808 views

How many words of memory map to the same cache entry?

I am going over some practice questions for the Major field exam and it asks: A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
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Computer Architecture: How to determine the bits of the address used to access the cache?

Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a ...
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2answers
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Interrupt enabling and disabling

While reading about interrupt mechanism, I understood that there is an IRQ signal line on the bus by which an I/O interface raise an interrupt request. There is an INTA signal line using which the ...
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Finding Worst and Best Case Hit Rate of a Cache Given Code

I'm doing some practice problems to study and came across this one: Consider a 8-way set associative cache with 64 B blocks, and 64 total blocks as part ofa 16 bit physical address. Imagine we use the ...
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1answer
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how does the program change the clock speed of the processor?

bios is a program that checks all devices and starts the bootloader. but how does the CPU sync with the motherboard if the CPU clock settings are stored in the BIOS? Does the BIOS have CPU clock ...
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1answer
34 views

Why cannot Operand forwarding remove all RAW hazards?

I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
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13answers
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What are GPUs bad at?

I understand that GPUs are generally used to do LOTS of calculations in parallel. I understand why we would want to parallelize processes in order to speed things up. However, GPUs aren't always ...
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Why is programmed I/O not suitable for high-speed data transfer?

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
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1answer
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Can synchronous data transfer be used for transferring large data in case of computer architecture and organization?

I am learning computer architecture and organization. I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization? I ...
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1answer
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In a single cycle datapath, do 'decode' and 'operand fetch' occur simultaneously?

After instruction has been fetched, does it go to control unit and register file at the same time or one after the other? For example if the control unit and register read both have 80ps delay, and we'...
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How does virtual and physical memory affect cache structure?

Working with a question that states: Consider a hypothetical machine in which physical address space is of 512 words and virtual address space is of 2048 words. The page size is 8 words. What is ...
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1answer
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Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it. Question was this: Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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1answer
182 views

What is the purpose of a single input, single output, bidirectional shift register?

(source: edu.au) This is the sort of bidirectional shift register, I'm talking about. I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
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3answers
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Speed of a microprocessor

I was just wondering why are are new generation microprocessors faster at the same clock speed as the old ones. For instance a 2.66Ghz dual core i5 is faster than the a device with clock speed of 2....
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1answer
55 views

What does “associative” exactly mean in “n-way set-associative cache”?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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1answer
292 views

CRC computation speed vs polynomials features

I tried to find information about how features of a CRC polynomials influence computation speed of implementations. It is obvious that (depending from the CPU architecture the algorithm runs on) ...
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2answers
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Adding two numbers in base 2(floating point) vs Multiplying two numbers in base 2(floating point)

Is it true that adding two numbers in base 2 is more complex than multiplying them? If so can someone please explain why this is the case?
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Is it possible to transmit bits digitally?

I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
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AMBIGUOUS AND UNAMBIGUOUS GRAMMAR [closed]

Can someone answer this for me? you need to do is derive the parse trees applicable for the following ambiguous grammar. Re-write it's unambiguous grammar and derive the parse tree. • S → aSbS l ...
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20 views

Transactional memory

I would like to understand what role does Transactional memory plays in memory organization, I know that To allow for more efficient parallel programming with higher performance, processor implements ...
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Calculate time needed to transfer data from the HDD

The ans of a student states that the ans is 0.0327 but idk know to get that ans. Maybe that ans is wrong too. Pls help
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1answer
40 views

Manipulating stack pointer in assembly

I have written an assembly program to store digits in a stack. And to print the digits I have used loop2: mov ah,2 int 21h sub cl,1 jnz loop2 But this would only ...
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1answer
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Dividing EX stage of a pipeline into EX1 and EX2 stages

There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be: In the five stage pipeline with forwarding support to EX, the first operand of ALU ...
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Cache Mapping Scheme

I am trying to solve the following problem: Consider a computer with a byte-addressable memory. A 64-bit memory address is divided as follows for cache processing. First, the 16 low-order bits are ...
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2answers
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Harvard processor structure

In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
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1answer
25 views

When the stall is actually going to happen?

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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1answer
417 views

What is memory model in computer organization?

I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking ...
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1answer
2k views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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Why did Apple include dedicated a neural network “processor” in standard consumer products?

Not sure if this is the right place, but I guess it is better than Reddit and I couldn't find any discussion. I was wondering why Apple include a neural network "processor" and can't help ...
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Cache consistency in uniprocessor system

In a uniprocessor system, can we have a Cache consistency problem? For sure, it exists in a multiprocessor system. But I wonder if it exists in a uniprocessor system and in which scenario.
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317 views

What is a cache write miss?

I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393; The other key ...
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1answer
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Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
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Difference between multiprocessor and uniprocessor in terms of run-time system

In the book "Advanced computer architecture and parallel processing" (El-Rewini & Abd-El-Barr), there is a question in the exercises of chapter 1 that needs the reader to compare between ...
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The following problem Decidable? If a Turing Machine M, on input w, will M ever move its read/write head to the left? [duplicate]

Decidable? If a Turing Machine M, on input w, will M ever move its read/write head to the left? I think the problem is decidable. We simulate M for |w| steps. Either it has moved to the left (accept) ...
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How is conditional jump implemented in the CPU?

After reading the question I'm still not sure how CPU does branching. I understand that we have an instruction counter which points to the current instruction. And after performing conditional jump it ...
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3answers
38k views

How do computers keep track of time?

How are computers able to tell the correct time and date every time? Whenever I close the computer (shut it down) all connections and processes inside stop. How is it that when I open the computer ...
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3answers
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Negative Numbers in 32 bit Floating Point IEEE Numbers

So I understand the logic behind converting positive decimal numbers to IEEE 32 bit floating numbers but I'm not completely sure behind the negative one's. If for example we have a decimal number say -...
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2answers
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Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
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What do “JAMZ”, “JAMN”, and “JMPC” stand for in Mic-1?

I am wondering what do JMPZ, JMPN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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4answers
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Can x86 Instruction Set be changed with microcode update?

How I understand microcode translate an instruction to microinstructions. And CPU has a unit that stores all possible of microinstructions. These microinstructions can be changed, because it load ...
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32 views

Effective Address for LDI instruction?

The effective address for the LDI instruction is the contents of the nearby memory location determined by the PC-Relative addressing mode. Let's assume that the address 0x5011 contains 1010 100 ...
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About NOP (NO Operation) for LC-3 instructions

0000 111 000011000 Will this instruction fail as a NOP? I think it is because it branches PC to a new address (incremented PC + 0x0018). If it were a branch that branches PC to itself like 0000 111 ...
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Select where the source operands are located for the following two LC-3 instructions:

Select where the source operands are located for the following two LC-3 instructions: 0001 111 010 0 00 011 1010 010 110011110 For source operands located in memory, distinguish the addressing mode ...
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Can old hardware be practically useful for CS problems of modern day?

Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
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How many cycles required in Instruction Level Parallelism?

L1: LD F1,0(R2) L2: LD F2,8(R2) L3: FADD F3,F1,F2 L4: SD F3,8(R2) If the instruction fetch for L1 starts at clock cycle 1, in which cycle the instruction L4 access memory to store the data? I am ...
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3answers
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Row Major Vs Column Major Order: 2D arrays access in programming languages

Programmers prefer accessing a 2D array in Row-Major Order rather than Column-Major Order, Why? Are there some advantages/benefits of accessing a 2D array in row-major as compare to column-major? ...
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What percentage should be parallelized?

While exploring about the 2-core system. The voltage decreases linearly with the frequency. The voltage may not decrease below 75% below the original voltage.This voltage is referred to as the voltage ...
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1answer
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Information theory of instruction set architecture design?

Information theory to a large extent deals with how to efficiently encode messages given a probability distribution over messages. Intuitively, it seems like we can think of machine instructions (or ...

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