Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
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How to find percentage of CPU time consumed during DMA operation?
Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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How does non-DMA transfers really work?
I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding:
disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
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New computer advertises 'No HDD' [closed]
It is my understanding that 'No HDD' mean 'no hard drive detected'. Why would Hewlett-Packard advertise that as a feature on a new HP All-in-One computer that I am considering purchasing? Isn't that ...
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How many words of memory map to the same cache entry?
I am going over some practice questions for the Major field exam and it asks:
A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
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Number of MUX required for Cache Mapping
I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...
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I/O Complexity Analysis with Memory Hierarchies
How to go about analysing the I/O complexity when there are multiple levels of memory involved? Looking up I/O complexity analyses returns papers such as this one, which generally assume for ...
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Best method to run an optimizing function millions of times
My goal is to find the local minimums of a smooth multivariate function $f_t(\vec y)$ for multiple values of $t$. I have created an algorithm $foo(t,\vec x)$ which returns the results of Newton's ...
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CPU interrupt load
I'm currently taking MIT 6.004 course. In one of the chapter regarding interrupts it says:
"There are several calculations we need to do when thinking about recurring interrupts.
The first is to ...
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About registers and IMUL
I do not know if this question makes sense
BUT
AX has two halves al and ah but the higher halves of EAX and RAX are not addressable.
When IMUL instruction is executed e.g. IMUL r/m16 the os uses ax ...
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Does cache hit time include both time to read a cache and time to write a cache?
For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data ...
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What is a procedure?
Non-computer scientist here, trying to understand what SICP (Structure and Interpretation of Computer Programs) means by a procedure, whether it matches the dictionary definition, and also how a ...
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Help with performance and speed-up question related to number of cores and their areas
There is a question in my exam that said:
Consider the following three processors (x, y, and z) that are all of varying areas. Assume that the single-thread performance of a core increases with the ...
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Page-to-Cache mapping
I have a computer architecture exam tomorrow and my professor gave us some questions for practice. I just need to clear some confusions.
The first question is: "a) In a Direct-Mapped Cache, ...
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Are there any radical approaches in CPU development?
I have a desktop PC with the CPU Intel I7-12700F with 180 TDP, the CPU fan Zalman CNPS10X extreme, and Windows 11 and my problem is that The CPU cooling causes much noise when simple tasks are being ...
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What do "JAMZ", "JAMN", and "JMPC" stand for in Mic-1?
I am wondering what do JAMZ, JAMN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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Concept of a Stream Device
In class, professor mentions that there are Stream and Storage devices. I mean to ask about Stream devices. I've also heard the terminology character devices.
On a Linux VM, the corresponding terminal ...
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Learn computer architecture and organisation via an oversimplified machine
I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
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Why does a 32 bit address only contain 1 byte, when 32 bits = 4 bytes?
I am really confused about it. I think 32 bits = 4 bytes but 32 bit address is only 1 bit.
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What is Address Sequencing?
Whenever I've come across this question whether on the internet or in my class everybody mentions the 4 address sequencing capabilities required in a control memory and the steps of address sequencing:...
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Execution of instruction in MIPS on various parts of the clock cycle
I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
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Does exist another models like CARDIAC, LMC and IPC?
I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
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How to calculate the size of main memory if the cache is 4-way set associative memory, cache memory size is 256KB and number of tag bits is 8
I'm trying to calculate the main memory size, and the only information given is the size of the cache, which is 256 KB, and the number of tag bits, which is 8. Cache is a 4-way set associative memory.
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How does a CPU jump to a instruction thats no longer in ram?
Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
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What is the purpose of a single input, single output, bidirectional shift register?
(source: edu.au)
This is the sort of bidirectional shift register, I'm talking about.
I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
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How is an Assembly Language Processed by a CPU's Circuitry?
I'd like to have a bit more understanding of how, on a circuitry/hardware level, an assembler program works.
I think I have a very broad-brush understanding of how a CPU would process machine code on ...
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Is this how endianess work relative to memory?
So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things.
Here is how I look at ...
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In the next ten years, what modifications to hardware architecture do you anticipate being made to enhance machine learning performance?
How do you believe prominent deep learning ASIC makers such as Nvidia and Google will alter their hardware design over the next decade to meet the exponentially expanding need for extra computing to ...
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How is the memory address structured when the number of blocks per cache set is not a power of 2?
When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization:
$$Address = TAG|...
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Load and Store Data hazard problem in 5-stages pipeline
Hi everyone and first of all thank you for been reading.
I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction.
(Assume that we're working ...
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Formal proof for in-balanced pipeline throughput
It is a well known fact, the throughput of a given compute pipeline (say, CPU instruction pipeline) is determined by its "slow" segment.
All the resources I've seen so far, demonstrates this ...
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which devices use parity checking?
I've just started learning computer architectures and I'm having trouble understanding where these are used.
I know that parity checking is testing for accurate data transmission between nodes in a ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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MIPS limited dual issue
Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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When the stall is actually going to happen?
Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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Greater than or equal to operation (32-bit ALU)
I'm trying to construct a greater than or equal to operation by adding some logic gates or building blocks (i.e. multiplexor and decoder) to my current 32-bit ALU
I'm not quite sure how to do this ...
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How does the Program Counter work?
I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction.
But now my question is, how do you ...
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Detecting Data and Control Hazards for a mips 5 stage pipeline
I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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How to design a simpler Version of CARDIAC (Cardboard Illustrative Aid to Computers)?
I'm trying to make a simpler version of CARDIAC for only performing addition. Now, I am encountering several problems in making something similar and looking for some ideas (I'm new to Computer ...
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How do I compute the address of the next element?
I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
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MIPS pipeline: choosing between slowing down a stage and adding a new stage
Suppose a new, more complicated, instruction is desired for this
simple pipelined MIPS processor. Suppose, also, it could be
implemented by either (a) adding new logic to the execute stage of the
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Why does CLRS refer to the disk parts as pages rather than blocks?
I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters:
In order to ...
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Pipelining without operand forwarding
I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l)
One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
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How a computer works?
I know that a computer can be mechanical, screws/nuts or even water/pipes. Of course, it would be slow and big, but it doesn't have to be electric, transistors, etc. How can a machine like this do all ...
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Why does the branch instruction stall at fetch?
Here is a problem (C.1.c) from the famous Hennessey & Patterson book
I'm struggling with. The following code fragment should be scheduled
on a five-stage MIPS CPU with "full forwarding and ...
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Calculate Stages in Non-Pipelined Processor
I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :-
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Is it possible to transmit bits digitally?
I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
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What is a cache write miss?
I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393;
The other key ...
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Within the set of signed integers representable by a bit string of length n, are any two elements equivalent to each other mod 2^n?
Donald Knuth's The Art of Computer Programming, Volume 1 Fascicle 1 contains the following exercise:
If $\alpha$ is any string of 0s and 1s, let $\operatorname{s}(\alpha)$ and $\operatorname{u}(\...
