Skip to main content

Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

Filter by
Sorted by
Tagged with
0 votes
1 answer
140 views

How do I compute the address of the next element?

I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
1 vote
1 answer
49 views

Why does ISA includes instruction for logical operation?

I'm a junior student in Electronic Engineering. Recently, I learned about Gödel's incompleteness theorem. One of the concepts related to this theorem is Gödel numbering, which shows that every logical ...
1 vote
1 answer
38 views

Desktop computing: who needs multi-threading, multi-processing; and how much?

I am currently running the KDE on OpenSuSE in a VirtualBox hosted by Windows 11 running on a processor with 14 cores. I gave Linux 4 CPUs to play with. So, I am aware of the need for some amount of ...
2 votes
1 answer
104 views

Why does CLRS refer to the disk parts as pages rather than blocks?

I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters: In order to ...
2 votes
1 answer
1k views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
-1 votes
1 answer
239 views

Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
1 vote
1 answer
1k views

What is Address Sequencing?

Whenever I've come across this question whether on the internet or in my class everybody mentions the 4 address sequencing capabilities required in a control memory and the steps of address sequencing:...
2 votes
1 answer
2k views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
1 vote
1 answer
228 views

How does non-DMA transfers really work?

I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding: disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
1 vote
2 answers
70 views

Why is the default page/block size 4 KiB?

Clearly, some empirical study on an older machine helped us choose a 4KiB page size to balance TLB hit rate and fragmentation. Modern hardware and operating systems support this size for backward ...
0 votes
3 answers
2k views

How many words of memory map to the same cache entry?

I am going over some practice questions for the Major field exam and it asks: A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
2 votes
1 answer
1k views

Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
0 votes
1 answer
31 views

Is it possible to completely remove a pre-installed OS from a manufactured computer?

I was told by my professor that when a computer is manufactured, it comes with an OS where the OS is installed in two different parts. The first part is physically "hardwired" (?) into the ...
0 votes
1 answer
26 views

Is there a service provided by the OS, which is NOT accessible by the terminal emulator?

Is there a service provided by the OS, which is NOT accessible by the terminal emulator? If so, how else would the user be accessing it? (My guess is, there wouldn't be since that would be silly. But ...
0 votes
1 answer
180 views

Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
1 vote
1 answer
33 views

Basic questions regarding a computer

I'm an Undergraduate CS student. My understanding of a "computer" is that it is simply a machine that can "carry out" a set of instructions. The set of instructions it can ever ...
0 votes
1 answer
134 views

Does cache hit time include both time to read a cache and time to write a cache?

For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data ...
27 votes
12 answers
19k views

Is a universal assembly language for all computers possible?

I would like to ask a few questions about Assembly language. My understanding is that it's very close to machine language, making it faster and more efficient. Since we have different computer ...
0 votes
1 answer
30 views

Is there a delay between two commands to read data from RAM?

Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
0 votes
1 answer
125 views

Why is the Program counter(PC) 12 bits and not 24 bits in IAS computer system?

Why is the Program counter(PC) 12 bits and not 24 bits in IAS computer system? PC is said to have next - instruction pair and an instruction has 12 bit adress and 20 bit opcode, so if it's a pair it ...
1 vote
1 answer
24 views

Floating Point to Integer Conversion (fcvt.*) hardware implementation

In the RISC-V specification, there is support for the conversion between floating point and integer numbers, in particular the fcvt* class of instructions. I'm wondering what the hardware ...
1 vote
2 answers
1k views

How does instruction set architecture affects clock rate?

According to the computer organization and design RISC-V 2nd edition 2020, section 1.5, the following table states that ISA affects clock rate. Hardware or software component Affects what? How? ...
1 vote
1 answer
73 views

Byte addressing and alignment

With byte addressing, the CPU can access a single byte. But how does this access happen during alignment? As I understand it, if a CPU needs to read an unaligned byte, it reads the word starting from ...
0 votes
1 answer
32 views

clock chip (not the CPU clock) replacement on my BEMER medical device

the 24 hour clock/timer on my BEMER PEMF device's microprocessor is keeping erratic time lately. Shortly after I reset to the correct time, it fails to keep accurate time. I'm wondering if exposing ...
3 votes
7 answers
14k views

How does the Program Counter work?

I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction. But now my question is, how do you ...
1 vote
1 answer
72 views

Execution of instruction in MIPS on various parts of the clock cycle

I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
1 vote
2 answers
260 views

Multi-threading : N cores = N times one core?

This question is about modern CPU architectures and multi-threading. I'm mainly interested in personal computers or servers having 2, 4, 8, 16... cores like for example an Intel core i7. I mean not a ...
0 votes
1 answer
1k views

How to calculate the size of main memory if the cache is 4-way set associative memory, cache memory size is 256KB and number of tag bits is 8

I'm trying to calculate the main memory size, and the only information given is the size of the cache, which is 256 KB, and the number of tag bits, which is 8. Cache is a 4-way set associative memory. ...
0 votes
2 answers
58 views

Why is ROM read only? And why do SSDs use it?

I was researching about SSDs and ended up going further and reading about how it uses flash technology which from what I gather is pretty much an EEPROM, which (I might be wrong on this) is just an ...
1 vote
2 answers
937 views

3 bit binary multiplier?

I have the following 2-bit binary multiplier (source: wikimedia.org) How can I modify this 2-bit binary multiplier to make it a 3-bit binary multiplier? I notice that there are 2 half-adders, and ...
2 votes
1 answer
291 views

What is the purpose of a single input, single output, bidirectional shift register?

(source: edu.au) This is the sort of bidirectional shift register, I'm talking about. I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
2 votes
1 answer
63 views

Measuring Cache Access Time

I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them: ...
2 votes
1 answer
55 views

How CPU uses wider address bus than register size?

i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). ...
1 vote
1 answer
93 views

MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?

I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following ...
3 votes
1 answer
3k views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
1 vote
2 answers
2k views

Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
1 vote
4 answers
319 views

Are all instructions eventually converted to zero-operand instructions?

Recently, my demonstrator said that all instructions are eventually converted to zero-operand instructions just before they get executed. yet another demonstrator said that this "doesn't make any ...
0 votes
1 answer
34 views

Are modern ram architectures (DDR4 or SDRAM) Multi-port or Dual-port?

So I recently learned about dual-port and multi-port RAM but I tried doing some research on modern RAM architectures and if they use it but I couldn't find anything on it.
0 votes
0 answers
16 views

Daughter-board multiplier

I am writing a program in TI Code Composer Studio assembly-only empty project using the MSP-EXP430FR6989. The assembly-only empty project uses MSP430 Assembler Code Template for use with TI Code ...
0 votes
1 answer
40 views

Formal proof for in-balanced pipeline throughput

It is a well known fact, the throughput of a given compute pipeline (say, CPU instruction pipeline) is determined by its "slow" segment. All the resources I've seen so far, demonstrates this ...
0 votes
1 answer
906 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
3 votes
1 answer
288 views

MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
0 votes
1 answer
1k views

Direct and Associate Cache - Offset, Index, and Tag

I have two questions: ...
0 votes
0 answers
25 views

Why do two pairs of identical DDR4 RAM not work together?

Several years ago, I tried to get two identical pairs of DDR4 RAM to run together in my computer. I have since bought a set of four, but I've always wondered why the RAM didn't work. Its been long ...
0 votes
2 answers
481 views

When the stall is actually going to happen?

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
0 votes
0 answers
54 views

Expected hit ratio for a cache

I am trying to understand how to approach the question below which is a coursework question. I understand that each memory request is 32 bits and so there will be 262144 requests. There are 42 blocks ...
0 votes
1 answer
19 views

The Atlas system word addresses

I'm reading about the Atlas operating system and I came across this: The Atlas system used a British computer with 48-bit words. Addresses were 24 bits but were encoded in decimal, which allowed 1 ...
2 votes
0 answers
41 views

Issue understanding how control signals are pipelined in a RISC architecture

I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding: ...
0 votes
0 answers
24 views

What is Representation Invariant?

I was the book "Introduction to Computation and Programming Using Python" and I stumbled upon the concept of representation invariant. What I understood is that the variables (and maybe ...
2 votes
1 answer
23 views

Memory addresses requested by CPU vs Memory Address Provided to DRAM

So, i just got through studying DRAM architecture. I learned that a row address, column address, bank number etc are provided to the DRAM during a read operation. Based on the address provided, 64 ...

1
2 3 4 5
23