Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How do I determine how many blocks have been replaced and what the hit ratio is of the following direct-mapped cache?

I have a direct-mapped cache with the following properties: Address size = 32 bits Cache block size = 8 words Entries = 32 So we can see the cache as a 32 by 8 table where the index selects the row ...
2 votes
1 answer
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What do "JAMZ", "JAMN", and "JMPC" stand for in Mic-1?

I am wondering what do JAMZ, JAMN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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Max RAM capacity on modern cpus

I am wondering why modern consumer cpu usually has 128GB memory limit when server cpu supports terabytes. 128GB is really not that much. Do they really can't handle more RAM? How wide is their address ...
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Why does this branch data hazard happen during the instruction decode stage?

Suppose I have the following MIPS code on a CPU with forwarding enabled: ...
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1 answer
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When the stall is actually going to happen?

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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2 answers
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What is memory model in computer organization?

I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking ...
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Are all CPU computations done using registers?

From my understanding, a CPU register is a temporary storage or working location built into the CPU itself. The CPU includes some functional units such as the ALU (which is part of the chip, as far as ...
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How many words of memory map to the same cache entry?

I am going over some practice questions for the Major field exam and it asks: A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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Why do we still use a Von Neumann Architecture in modern computers?

The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons. To this day the Von Neumann ...
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Does cache hit time include both time to read a cache and time to write a cache?

For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data ...
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4 answers
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Can computers only add?

So recently I've been involved in a discussion and I was told that literally the only thing computer can do is addition. Is that true? What about logic operations? Aren't they performerd by physical ...
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Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it. Question was this: Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 ...
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What is the purpose of a single input, single output, bidirectional shift register?

(source: edu.au) This is the sort of bidirectional shift register, I'm talking about. I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
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CRC computation speed vs polynomials features

I tried to find information about how features of a CRC polynomials influence computation speed of implementations. It is obvious that (depending from the CPU architecture the algorithm runs on) ...
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Macroinstruction programming changing instructions

I need the solutions to the two questions that are in the problem, they are difficult to understand please explain how do u get to the answers thanks.
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2 answers
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Is it possible to transmit bits digitally?

I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
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1 answer
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How was counted one second in computers

I would like to know how was counted 1 second in computers. I mean how machine can understand period of 1 second. Who and when resolved this problem, and more important how ?
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Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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How can this MIPS processor execute one instruction in one cycle?

I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris. At the end of the section the autor shows this MIPS processor and ...
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1 answer
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Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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If I open & connect with 1 protocol to every port (all 65535) can we still open another protocol socket?

I understand and have googled how TCP & UDP can work simultaneously BUT does this assume there are unused ports to dynamically allocate? So if all ports are used by TCP can UDP still connect & ...
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1 answer
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What does it mean unambiguously that a number is value 0 up to numerical precision?

I was reading that a quantity $x$ is $0$ upt to numerical precision. What does this statement formally mean -- especially in the context of numerical methods or real computers. I looked up in google ...
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Difficulty understanding how federation increases cache performance for databases?

I am studying system design for distributed systems and in this page (https://github.com/donnemartin/system-design-primer), one of the following advantages was mentioned for federation for databases ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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1 answer
618 views

Direct and Associate Cache - Offset, Index, and Tag

I have two questions: ...
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3 answers
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Is the statement "Control unit controls overall operations of computer." true or false

I was tutoring a grade 4 student about CPU and I got confused as there are also the other units of a cpu like arithmetic and logic unit and memory unit. So, is the above statement actually true even ...
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In Programming data types size are depends upon what?

In Programming there is different data types (int , cahr , bool , float ) and they have different sizes (1,2,4,8 .. Bytes) , and the size of data type are depends upon hardware or architecture of ...
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Assembly language addressing mode instructions

I am studying assembly language. I feel very difficult in understanding few instruction. ADD R1,R2,[R3] ADD R1, R2, R3 What is the difference between these two instructions. I think second instruction ...
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1 answer
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Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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3 answers
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Why is C still the fastest? Critique my take

A friend and I were surprised that C still has near-best performance among languages. I thought about why this is, and I wrote up a few paragraphs. I wonder if the friendly folks on CS stack could ...
2 votes
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How to design a simpler Version of CARDIAC (Cardboard Illustrative Aid to Computers)?

I'm trying to make a simpler version of CARDIAC for only performing addition. Now, I am encountering several problems in making something similar and looking for some ideas (I'm new to Computer ...
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Von Neumann mixed with Havard in modern CPU?

Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
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What is the difference between clock cycle and clock period?

I'm reading Computer Organization and Design Sixth edition by Patterson and they define clock speed as this: Almost all computers are constructed using a clock that determines when events take place ...
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Metrics on which Clock Cycles Per Instruction(CPI) depends

In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this: The term clock cycles per instruction, which is ...
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How do I compute the address of the next element?

I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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MIPS pipeline: choosing between slowing down a stage and adding a new stage

Suppose a new, more complicated, instruction is desired for this simple pipelined MIPS processor. Suppose, also, it could be implemented by either (a) adding new logic to the execute stage of the ...
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Why does CLRS refer to the disk parts as pages rather than blocks?

I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters: In order to ...
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Performance of CPU with two caches

I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this Cache L1 ...
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1 answer
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preprocessing or real time for magnification of portions of video

Im new at CS and would like to gather preliminary information to approach an interactive art project. I want to construct a grid of videos - think about a matrix M = m x n where Mi,j is a video that ...
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1 answer
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Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
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how 16 bits address lines address 64KB?

" The 8080 was an 8-bit CPU, meaning it processed 8 bits of information at a time. However, it had 16 address lines coming out of it. The ‘‘bitness’’ of a CPU—how many bits wide its general-purpose ...
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How bits translated into text on the screen?

recently i started studying computer science and computer graphics, and one question really haunts me. Mby someone can explain this. How bit patterns become translated into (for example ) text. I know ...
2 votes
1 answer
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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2 answers
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How are instructions from software sent to digital circuit in cpu?

I am studying computer architecture in my university and there is something that's troubling me. I get the bigger picture of how instructions are executed in the fetch - execute cycle and the complete ...
2 votes
1 answer
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Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
11 votes
3 answers
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Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux

I'm reading CSAPP and couldn't wrap my head around this part: Summary of what the section says: Intel Core i7 support a 48-bit virtual address space and 52-bit physical address space. Core i7 uses a ...
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What is meant by capability-based addressing and capability-system model?

What is meant by capability-based addressing and capability-system model? For context, I'm trying to understand the paper on Capability Hardware Enhanced RISC Instructions (CHERI). I haven't been ...
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Computations in sequential implementation of Y86 instructions

I try to write down computation for Y86 instruction: ...
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2 answers
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Really confused about latency with pipelining

I finished watching a video about pipelining https://www.youtube.com/watch?v=eVRdfl4zxfI which I thought made sense. Latency is the amount of time it takes to complete each instruction. Even with ...

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