Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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30
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6answers
37k views

Why Do Computers Use the Binary Number System (0,1)?

Why Do Computers Use the Binary Number System (0,1)? Why don't they use Ternary Number System (0,1,2) or any other number system instead?
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6answers
5k views

How does a computer work?

I have been a computer nerd for many many years. I can program in quite a few languages, and I can even build them. I sat down with a buddy the other day and asked how a computer actually takes ...
6
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1answer
18k views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given $3, 180, 43, 2,...
4
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7answers
6k views

Ternary processing instead of Binary

Most of the computers available today are designed to work with binary system. It comes from the fact that information comes in two natural form, true or false. We humans accept another form of ...
16
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7answers
15k views

How is a program executed at the CPU level?

I know this is a very common question. But I have a different angle in my mind. I will just try to articulate it here. From what I know, every instruction that a CPU executes, is in machine language ...
10
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4answers
11k views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
5
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2answers
18k views

What is difference between architecture and microarchitecture?

I am studying computer architecture. I would like to know the difference between the terms "computer architecture" and "microarchitecture".
6
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2answers
886 views

Why is word-addressable the exception, not the rule?

As stated on Wikipedia: Most modern computers are byte-addressable instead of word-addressable. Why is this case? Since the CPU processes words (of predominantly 64 bits or 8 bytes) now, wouldn't ...
2
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0answers
2k views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
0
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0answers
85 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
57
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2answers
25k views

What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
23
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5answers
274k views

How to calculate the number of tag, index and offset bits of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
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4answers
4k views

why do CPU architectures use a flags register (advantages?)

Some CPUs have a flags register (ARM,x86,...), others don't (MIPS,...). What's the advantage of having a CMP instruction to update the flags register followed by a branch instruction instead of using ...
3
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2answers
6k views

Is word size, the size of a memory location? the size of the data bus? or the cpu register size?

Is word size, the size of a memory location? the size of the data bus? or the cpu register size? Suppose you have a computer, memory address #0 has byte AB memory address #1 has byte F3 memory ...
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2answers
19k views

Differences between SISD, SIMD and MIMD architecture (Flynn classification)

I have a problem with classifying certain CPUs to the proper classes of Flynn's Taxonomy. 1. Zilog Z80 According to this article on Sega Retro, Z80 has limited abilities to be classified as SIMD: ...
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2answers
14k views

calculate the effective (average) access time (E AT) of this system

A computer with a single cache (access time 40ns) and main memory (access time 200ns) also uses the hard disk (average access time 0.02 ms) for virtual memory pages. If it is found that the cache hit ...
4
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2answers
460 views

Why is Computer Architecture in $2^n$ bits?

I have always wondered why is computer architecture in $2^n$ bits. We have 8 / 16 / 32 / 64-bit microprocessors or for that matter other parts of computer are also in power of 2 bits. The only logic ...
2
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1answer
143 views

Is there code below microcode?

Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
2
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2answers
2k views

What is the system's mean time to failure?

I have the following homework problem: A 10 TB disk drive has an MTTF of 6,000,000 hours. How much data can we store in a system comprised of these disks, if we want the system MTTF to be at least 1....
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1answer
1k views

What is happening in this part of the LC3? [closed]

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
0
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2answers
312 views

Address bus and memory

If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it? What I'm trying to ask is that do all the 65536 locations ...
89
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13answers
23k views

What are GPUs bad at?

I understand that GPUs are generally used to do LOTS of calculations in parallel. I understand why we would want to parallelize processes in order to speed things up. However, GPUs aren't always ...
55
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7answers
30k views

Why does a processor have 32 registers?

I've always wondered why processors stopped at 32 registers. It's by far the fastest piece of the machine, why not just make bigger processors with more registers? Wouldn't that mean less going to the ...
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11answers
15k views

Is a universal assembly language for all computers possible?

I would like to ask a few questions about Assembly language. My understanding is that it's very close to machine language, making it faster and more efficient. Since we have different computer ...
15
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1answer
20k views

How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
38
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2answers
2k views

Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...
24
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7answers
11k views

Why floating point representation uses a sign bit instead of 2's complement to indicate negative numbers

Consider a fixed point representation which can be regarded as a degenerate case of a floating number. It is entirely possible to use 2's complement for negative numbers. But why is a sign bit ...
8
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2answers
20k views

Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
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2answers
9k views

What is instruction throughput and instruction latency?

I was reading an article on an alternative method of modulo reduction and i couldn't understand the following excerpt (Those in bold) : "A single 32-bit division on a recent x64 processor has a ...
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4answers
9k views

Why do we need so many transistors in a chip, and how are they managed?

My knowledge is very vague as all we have are visual diagrams etc, but we have memory address and registers, the ALU being the heart(apparently). Single core CPUs process one instruction at a time ...
6
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1answer
2k views

Why is a superscalar processor SIMD?

From http://en.wikipedia.org/wiki/Superscalar In Flynn's taxonomy, a single-core superscalar processor is classified as an SIMD processor (Single Instructions, Multiple Data), Flynn's taxonomy ...
20
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3answers
991 views

Are today's massive parallel processing units able to run cellular automata efficiently?

I wonder whether the massively parallel computation units provided in graphic cards nowadays (one that is programmable in OpenCL, for example) are good enough to simulate 1D cellular automata (or ...
19
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6answers
3k views

How can I academically say that 'one computer is slower than the other'?

I'm writing a research paper and I have to basically say that one microcontroller is slower than an other microprocessor. However, I'm worried that simply saying that it's 'slower' wouldn't be ...
3
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3answers
7k views

Moore's law and Clock Speed

This figure says according to moore's law number of transistors doubles about two years. but clock speed, power flattening after given stage. can anyone describe the reasons this flattening in clock-...
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4answers
4k views

CPU frequency per year

I know that since ~2004, Moore's law stopped working for CPU clock speed. I'm looking for a graph showing this, but am unable to find it: most charts out there show the transistor count or the ...
12
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2answers
3k views

Do computers actually use carry-lookahead adders?

There are plenty of details about carry lookahead adders such as Kogge-Stone, Lander-Fischer, etc. in college CS courses. They are described as "common in the industry". However, I can't find any ...
9
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2answers
48k views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
4
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3answers
9k views

Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: <...
2
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2answers
522 views

Why does x86 has explicit register definitions, and RISC's doesn't?

For example, on x86, we have a set of general registers, each named to the function it carries out. We have an Accumulator, which is a storage for a results of different fixed point operations, we ...
14
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1answer
378 views

Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
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3answers
1k views

Why is the CPU Involved During Keyboard Echo?

I'm currently studying for a computer science exam, and I've come across a concept that has me somewhat stumped. When one types a key on the keyboard, an ASCII character is transmitted to the CPU. ...
6
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3answers
935 views

Where should I start to understand how computers work? [duplicate]

I am interested in how computers work but I have no idea how the concept of 0's and 1's converts to making possible for people to control a computer by programming. I would like to understand from ...
6
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3answers
5k views

What is Simultaneous Multithreading

I come from an electronics background. I know that there are three types of implementations of multithreading (see Computer Architecture: A Quantitative Approach, 5th Edition): Fine-grain ...
3
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3answers
5k views

How exactly the “load word” instruction loads from RAM?

PS: MIPS architecture This is a model of a memory RAM of 4GB: it has 4,294,967,295 addresses, and each address has 32 bits. Can somebody tell me why the load word instruction needs an offset to the ...
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2answers
586 views

Explanation for indirect addressing

While reading about minimal instruction set computer I found out that one needs at least (for example) the ability to increment or decrement the value stored in register, a test for zero and a jump. A ...
8
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1answer
22k views

What is the exact difference between a latch & a flipflop?

From what I have understood : A Flip Flop is a clocked latch i.e. flip flop = latch + clock Latch continuously checks for inputs & changes the output whenever there is a change in input Flip Flop ...
7
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3answers
2k views

CPU and GPU differences

What is the difference between a single processing unit of CPU and single processing unit of GPU?  Most places I've come along on the internet cover the high level differences between the two. I want ...
4
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2answers
609 views

Can the Lambda Calculus or Turing Machines model signals, callbacks, sleep/wait, or buses?

I have a deep appreciation for formalisms like the Turing Machine and the $\lambda$-Calculus, and enjoy studying them and learning more about how they relate to physical computers. I am now learning ...
4
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3answers
497 views

Why are there only NOR and NAND flashes?

According to my lecture and wikipedia NOR and NAND flashes are the most common used. However there isn't really explained why people decided to use these logic gates instead of others. Can someone ...
3
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1answer
1k views

How does the CPU know to get data from or send data to a peripheral device?

We were talking today, in Intro to Programming, about machine language. I know it's a bunch of 0's and 1's. Let's say I compile the following C++ program on an x86 machine: ...