Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
207
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Is there any defined programming model for 'Self-Learning' NPUs?
Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth.
IBM is also working on a brain inspired chip under Synapse program.
Standford's Neurogrid might be a similar example.
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How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
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Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?
In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
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Detecting Data and Control Hazards for a mips 5 stage pipeline
I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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Load and Store Data hazard problem in 5-stages pipeline
Hi everyone and first of all thank you for been reading.
I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction.
(Assume that we're working ...
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Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?
I have a question where I am asked to find the size of a cache. I am given the following info:
a) the length of a memory address
b) the number of bits for offset, index, and tag fields.
I know I ...
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3
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1
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MIPS limited dual issue
Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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Does exist another models like CARDIAC, LMC and IPC?
I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
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Belt-based mechanical computers
I've seen a lot of mechanical computers based on gears and rigid rods, but none so far that consequently use belts (not chains) for transmission of information.
Belts allow for easy negation (by ...
2
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Von Neumann mixed with Havard in modern CPU?
Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
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Why does CLRS refer to the disk parts as pages rather than blocks?
I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters:
In order to ...
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What do "JAMZ", "JAMN", and "JMPC" stand for in Mic-1?
I am wondering what do JAMZ, JAMN, and JMPC stand for in Tanenbaum's Mic-1 architecture. I ...
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Confused with an Instruction Cycle question
Here's the question
The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
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Finding the timestamps of processes implementing Lamport's clocks
I have been asked this question, but don't know how to go about answering it.
Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
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What is "orthogonality" in the context of Instruction Encoding?
What does it mean by "orthogonality" in the context of Instruction Encoding?
Why CISC Architecture is orthogonal while RISC is not?
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Compiler optimization which does an SMT-like optimization in software?
Say I had two functions called one after the other:
...
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What is tag-only forced cache inclusion called?
Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data?
Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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Is there one or more Page Tables
I saw a question similar to this one, and it was answered but the answer was kind of vague and I'm looking for a little more detail than that. The question I'm referring to is this one.
The answer ...
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Single queue instruction issuing in computer architecture
I am working on this paper titled “the microarchitecture of superscalar processors by Smith and Sohi” and it says that there are 3 methods of organizing instruction queue. I know that the method “...
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Number of MUX required for Cache Mapping
I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...
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1
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How to find percentage of CPU time consumed during DMA operation?
Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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Pipelining without operand forwarding
I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l)
One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
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Where does the CPU scheduler sit in a layered OS design
In a layered approach to OS design, each layer can only access routines from the layers below itself.
For example, say I had two levels: memory management and the CPU scheduler
Where does the CPU ...
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Write-To-Read Relaxation in Cache Consistency
Write-to-Read Relaxation means that for a processor:
later reads can bypass earlier writes
But what does that mean?
What exactly is the difference between a read and a write for a Cache?
An ...
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CISC, RISC and anything else?
Is there a processor architecture that falls outside the CISC and RISC categories?
I'm vaguely familiar with RISC and CISC; my research thus far indicates that either a processor is RISC or CISC, ...
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How is the size of a register related to the size of primary memory?
I understand that registers are temporary storage compartments which (usually) hold 8 bits, or 1 byte, of information at a time. This information is sent from a register into the Central Processing ...
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Given a program which when executed spawns two concurrent processes : semaphore X : = 0 ; Is it possible for process P1 and P2 to starve?
Given below is a program which when executed spawns two concurrent processes:
...
2
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Why ternary computers like Setun didn't catch on?
Why ternary computers like Setun didn't become popular despite being cheaper and more reliable than binary computers, and also having important computational advantages? We could have had cheaper ...
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Will this address result in a cache hit or miss for these cache mapping functions?
The Problem: A CPU produces the following sequence of read addresses in hex.
Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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Future register file in computer architecture
Results from the execution units are written into the future file when they complete (may be out-of-order). Upon operand fetching, you fetch from the future file and not the architectural register ...
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Is there a prefered name for the “effective access time” formula?
Any CS class about caches will at some point address this classical formula (or a variant of it)
Effective_access_time = hit_time + miss_penalty * miss_rate
My ...
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How does RAID-5 algorithm locate the right device?
Please consider the following diagram of a RAID-5 array (Ignore the gray background):
Now, given a logical address, how can one return the device number (0-3)?
For example, DeviceByLogicalSector(50) ...
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2
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How to design a simpler Version of CARDIAC (Cardboard Illustrative Aid to Computers)?
I'm trying to make a simpler version of CARDIAC for only performing addition. Now, I am encountering several problems in making something similar and looking for some ideas (I'm new to Computer ...
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Learn computer architecture and organisation via an oversimplified machine
I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
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How does non-DMA transfers really work?
I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding:
disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
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Execution of instruction in MIPS on various parts of the clock cycle
I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
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How is the memory address structured when the number of blocks per cache set is not a power of 2?
When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization:
$$Address = TAG|...
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Is this how endianess work relative to memory?
So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things.
Here is how I look at ...
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Tomasulo's Algorithm: Is there one reservation station per functional unit?
In Tomasulo's algorithm, is there only one reservation station per functional unit (even with multiple same-function FUs like, say, 3 adders)? Can there be more?
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What does it mean to have the processor ignore interrupt request line?
I was reading a textbook on COA, it says
If the processor is going to ignore the interrupt request line till the execution of the first instruction of the ISR, how will it know which device to ...
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which devices use parity checking?
I've just started learning computer architectures and I'm having trouble understanding where these are used.
I know that parity checking is testing for accurate data transmission between nodes in a ...
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Is there any video where I can see how different data rates impact daily activities?
I've been learning about data speed and width and the rate of the bus where information is transmitted between components. But I can't see or understand how fast is the transmission.
For example, in ...
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Why place of MA in MB then copy from MB to IR rather than going straight from MA to IR
During the fetch stage of the fetch-execute cycle, why are the contents of the cell whose address is in the MA (memory address register) placed in MB (memory buffer) then copied to IR (instruction ...
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How the data is transferred from main memory to hard disk?
I understand that data is transferred from the main memory to the CPU and vise versa using the data bus. But, I am unable to understand, how the data is being transferred from the main memory to the ...
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How can DRAM memory speeds be improved?
What are some ways with which we can improve the speed of dynamic RAMs?
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system architecture or software architecture
I was trying to get started with a small project but I quickly realized I had to do more research on the subject.
Suppose, when creating a site, in production, there's a certain structure how the ...
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Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register
I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
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How does virtual and physical memory affect cache structure?
Working with a question that states:
Consider a hypothetical machine in which physical address space is
of 512 words and virtual address space is of 2048 words. The page
size is 8 words. What is ...
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Can old hardware be practically useful for CS problems of modern day?
Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
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K-Map Reduction Grouping Question
I have a simple question regarding reduction using K-Maps.
My professor gave this example:
While I somewhat understand that we can only group quantities of base 2 numbers, why did my professor group ...
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