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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Is there any defined programming model for 'Self-Learning' NPUs?

Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth. IBM is also working on a brain inspired chip under Synapse program. Standford's Neurogrid might be a similar example. ...
xsnk's user avatar
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4 votes
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Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?

In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
Gabriel Fair's user avatar
3 votes
1 answer
3k views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
apcarry 's user avatar
3 votes
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243 views

Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
jeanette's user avatar
3 votes
1 answer
288 views

MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
user3901167's user avatar
2 votes
1 answer
62 views

Measuring Cache Access Time

I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them: ...
Agustín Núñez's user avatar
2 votes
0 answers
41 views

Issue understanding how control signals are pipelined in a RISC architecture

I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding: ...
Micronuno's user avatar
2 votes
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Does exist another models like CARDIAC, LMC and IPC?

I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
Osvaldo Santos's user avatar
2 votes
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Belt-based mechanical computers

I've seen a lot of mechanical computers based on gears and rigid rods, but none so far that consequently use belts (not chains) for transmission of information. Belts allow for easy negation (by ...
Hans-Peter Stricker's user avatar
2 votes
0 answers
82 views

Von Neumann mixed with Havard in modern CPU?

Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
kruemi's user avatar
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2 votes
1 answer
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Why does CLRS refer to the disk parts as pages rather than blocks?

I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters: In order to ...
2xMax's user avatar
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
Abhishek Ghosh's user avatar
2 votes
0 answers
171 views

Confused with an Instruction Cycle question

Here's the question The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
Sketchy's user avatar
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2 votes
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Finding the timestamps of processes implementing Lamport's clocks

I have been asked this question, but don't know how to go about answering it. Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
Agent smith 2.0's user avatar
2 votes
0 answers
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What is "orthogonality" in the context of Instruction Encoding?

What does it mean by "orthogonality" in the context of Instruction Encoding? Why CISC Architecture is orthogonal while RISC is not?
David Roonie's user avatar
2 votes
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62 views

Compiler optimization which does an SMT-like optimization in software?

Say I had two functions called one after the other: ...
user130558's user avatar
2 votes
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199 views

Regarding Amdahl's balanced system law

One of the paper titled "Rules of Thumb in Data Engineering" (Jim Gray et. el.) mentions some calculations based on Amdahl's balanced system law. Link to paper: https://www.microsoft.com/en-us/...
user108161's user avatar
2 votes
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40 views

What is tag-only forced cache inclusion called?

Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data? Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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2 votes
0 answers
75 views

Is there one or more Page Tables

I saw a question similar to this one, and it was answered but the answer was kind of vague and I'm looking for a little more detail than that. The question I'm referring to is this one. The answer ...
Koy's user avatar
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0 answers
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Single queue instruction issuing in computer architecture

I am working on this paper titled “the microarchitecture of superscalar processors by Smith and Sohi” and it says that there are 3 methods of organizing instruction queue. I know that the method “...
Navide's user avatar
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2 votes
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Difference between Response time, Execution time, and CPU time

I studied Computer Architecture from David A. Patterson and have came across the idea of Response time. Response time also called Execution time. The total time required for the computer to ...
F.C. Akhi's user avatar
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2 votes
1 answer
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Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
Random Integer's user avatar
2 votes
1 answer
2k views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
Sourajit's user avatar
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2 votes
1 answer
1k views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
Gokul's user avatar
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2 votes
0 answers
103 views

Where does the CPU scheduler sit in a layered OS design

In a layered approach to OS design, each layer can only access routines from the layers below itself. For example, say I had two levels: memory management and the CPU scheduler Where does the CPU ...
ethane's user avatar
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2 votes
0 answers
106 views

Write-To-Read Relaxation in Cache Consistency

Write-to-Read Relaxation means that for a processor: later reads can bypass earlier writes But what does that mean? What exactly is the difference between a read and a write for a Cache? An ...
Seen's user avatar
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2 votes
1 answer
291 views

What is the purpose of a single input, single output, bidirectional shift register?

(source: edu.au) This is the sort of bidirectional shift register, I'm talking about. I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
Physco111's user avatar
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2 votes
0 answers
236 views

CISC, RISC and anything else?

Is there a processor architecture that falls outside the CISC and RISC categories? I'm vaguely familiar with RISC and CISC; my research thus far indicates that either a processor is RISC or CISC, ...
Shrout1's user avatar
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2 votes
0 answers
1k views

How is the size of a register related to the size of primary memory?

I understand that registers are temporary storage compartments which (usually) hold 8 bits, or 1 byte, of information at a time. This information is sent from a register into the Central Processing ...
Valentine's user avatar
2 votes
0 answers
601 views

Given a program which when executed spawns two concurrent processes : semaphore X : = 0 ; Is it possible for process P1 and P2 to starve?

Given below is a program which when executed spawns two concurrent processes: ...
Mithlesh Upadhyay's user avatar
2 votes
0 answers
1k views

Why ternary computers like Setun didn't catch on?

Why ternary computers like Setun didn't become popular despite being cheaper and more reliable than binary computers, and also having important computational advantages? We could have had cheaper ...
arctifox's user avatar
2 votes
0 answers
2k views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
committedandroider's user avatar
2 votes
0 answers
517 views

Future register file in computer architecture

Results from the execution units are written into the future file when they complete (may be out-of-order). Upon operand fetching, you fetch from the future file and not the architectural register ...
gilianzz's user avatar
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2 votes
0 answers
210 views

Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
Gyom's user avatar
  • 121
2 votes
1 answer
159 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50) ...
Arbel's user avatar
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1 vote
1 answer
31 views

Basic questions regarding a computer

I'm an Undergraduate CS student. My understanding of a "computer" is that it is simply a machine that can "carry out" a set of instructions. The set of instructions it can ever ...
user1514263's user avatar
1 vote
2 answers
69 views

Why is the default page/block size 4 KiB?

Clearly, some empirical study on an older machine helped us choose a 4KiB page size to balance TLB hit rate and fragmentation. Modern hardware and operating systems support this size for backward ...
idle_cycles's user avatar
1 vote
0 answers
39 views

Load Store Hazard

I recently had an interview to identify all of the hazards in the following instruction set. I was told by the interviewer that there was some hazard between instructions i3 and i4 and it's not a RAW ...
johnbon's user avatar
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1 vote
0 answers
20 views

How can I connect a drive to a 16 bit custom intel 8088 system?

I'm embarking on a long-term project, aiming to build a computer based on the Intel 8088 architecture. This venture provides an excellent opportunity to deepen my understanding of computer hardware ...
Grizzly's user avatar
  • 11
1 vote
0 answers
33 views

Learn computer architecture and organisation via an oversimplified machine

I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University. Toy ...
anurag's user avatar
  • 111
1 vote
1 answer
227 views

How does non-DMA transfers really work?

I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding: disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
user129393192's user avatar
1 vote
1 answer
72 views

Execution of instruction in MIPS on various parts of the clock cycle

I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
ronak jain's user avatar
1 vote
0 answers
56 views

Tomasulo's Algorithm: Is there one reservation station per functional unit?

In Tomasulo's algorithm, is there only one reservation station per functional unit (even with multiple same-function FUs like, say, 3 adders)? Can there be more?
zach's user avatar
  • 11
1 vote
0 answers
55 views

What does it mean to have the processor ignore interrupt request line?

I was reading a textbook on COA, it says If the processor is going to ignore the interrupt request line till the execution of the first instruction of the ISR, how will it know which device to ...
Jacob P.J's user avatar
1 vote
0 answers
24 views

Is there any video where I can see how different data rates impact daily activities?

I've been learning about data speed and width and the rate of the bus where information is transmitted between components. But I can't see or understand how fast is the transmission. For example, in ...
gurung's user avatar
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1 vote
0 answers
12 views

Why place of MA in MB then copy from MB to IR rather than going straight from MA to IR

During the fetch stage of the fetch-execute cycle, why are the contents of the cell whose address is in the MA (memory address register) placed in MB (memory buffer) then copied to IR (instruction ...
amroman's user avatar
  • 11
1 vote
0 answers
474 views

How the data is transferred from main memory to hard disk?

I understand that data is transferred from the main memory to the CPU and vise versa using the data bus. But, I am unable to understand, how the data is being transferred from the main memory to the ...
Twinkle's user avatar
  • 11
1 vote
0 answers
41 views

How can DRAM memory speeds be improved?

What are some ways with which we can improve the speed of dynamic RAMs?
TheInquirer's user avatar
1 vote
0 answers
33 views

system architecture or software architecture

I was trying to get started with a small project but I quickly realized I had to do more research on the subject. Suppose, when creating a site, in production, there's a certain structure how the ...
BumbleBee's user avatar
1 vote
0 answers
158 views

Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
Hoang Nam's user avatar
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