Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

220 questions with no upvoted or accepted answers
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Is there any defined programming model for 'Self-Learning' NPUs?

Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth. IBM is also working on a brain inspired chip under Synapse program. Standford's Neurogrid might be a similar example. ...
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Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?

In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
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Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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50 views

Confused with an Instruction Cycle question

Here's the question The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
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Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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Finding the timestamps of processes implementing Lamport's clocks

I have been asked this question, but don't know how to go about answering it. Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
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2answers
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Really confused about latency with pipelining

I finished watching a video about pipelining https://www.youtube.com/watch?v=eVRdfl4zxfI which I thought made sense. Latency is the amount of time it takes to complete each instruction. Even with ...
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55 views

What is “orthogonality” in the context of Instruction Encoding?

What does it mean by "orthogonality" in the context of Instruction Encoding? Why CISC Architecture is orthogonal while RISC is not?
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Compiler optimization which does an SMT-like optimization in software?

Say I had two functions called one after the other: ...
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24 views

What is tag-only forced cache inclusion called?

Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data? Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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Is there one or more Page Tables

I saw a question similar to this one, and it was answered but the answer was kind of vague and I'm looking for a little more detail than that. The question I'm referring to is this one. The answer ...
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1answer
637 views

Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
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1answer
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Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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Where does the CPU scheduler sit in a layered OS design

In a layered approach to OS design, each layer can only access routines from the layers below itself. For example, say I had two levels: memory management and the CPU scheduler Where does the CPU ...
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Write-To-Read Relaxation in Cache Consistency

Write-to-Read Relaxation means that for a processor: later reads can bypass earlier writes But what does that mean? What exactly is the difference between a read and a write for a Cache? An ...
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201 views

CISC, RISC and anything else?

Is there a processor architecture that falls outside the CISC and RISC categories? I'm vaguely familiar with RISC and CISC; my research thus far indicates that either a processor is RISC or CISC, ...
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How is the size of a register related to the size of primary memory?

I understand that registers are temporary storage compartments which (usually) hold 8 bits, or 1 byte, of information at a time. This information is sent from a register into the Central Processing ...
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435 views

Given a program which when executed spawns two concurrent processes : semaphore X : = 0 ; Is it possible for process P1 and P2 to starve?

Given below is a program which when executed spawns two concurrent processes: ...
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954 views

Why ternary computers like Setun didn't catch on?

Why ternary computers like Setun didn't become popular despite being cheaper and more reliable than binary computers, and also having important computational advantages? We could have had cheaper ...
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1answer
479 views

How to design a simpler Version of CARDIAC (Cardboard Illustrative Aid to Computers)?

I'm trying to make a simpler version of CARDIAC for only performing addition. Now, I am encountering several problems in making something similar and looking for some ideas (I'm new to Computer ...
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2k views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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373 views

Future register file in computer architecture

Results from the execution units are written into the future file when they complete (may be out-of-order). Upon operand fetching, you fetch from the future file and not the architectural register ...
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230 views

MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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207 views

Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
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1answer
134 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50) ...
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Transactional memory

I would like to understand what role does Transactional memory plays in memory organization, I know that To allow for more efficient parallel programming with higher performance, processor implements ...
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25 views

How does virtual and physical memory affect cache structure?

Working with a question that states: Consider a hypothetical machine in which physical address space is of 512 words and virtual address space is of 2048 words. The page size is 8 words. What is ...
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2answers
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Adding two numbers in base 2(floating point) vs Multiplying two numbers in base 2(floating point)

Is it true that adding two numbers in base 2 is more complex than multiplying them? If so can someone please explain why this is the case?
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Can old hardware be practically useful for CS problems of modern day?

Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
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K-Map Reduction Grouping Question

I have a simple question regarding reduction using K-Maps. My professor gave this example: While I somewhat understand that we can only group quantities of base 2 numbers, why did my professor group ...
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Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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24 views

Were boolean logic used in the analog computers?

I began a simple collection of the events behind todays computers. My knowledege in these fields is so limited, and I read: "In the 1930s and working independently, American electronic engineer ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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2answers
79 views

Harvard processor structure

In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
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1answer
55 views

What does “associative” exactly mean in “n-way set-associative cache”?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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22 views

Output Dependency using Delta Test

Is there any way to find output dependency using delta test? I know that we can perform flow and anti dependence test using delta test, but to find output dependency for such case? For example say if ...
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Is there any research on allocating memory across multiple non-contiguous regions?

From my understanding, malloc and-the-like allocate contiguous blocks of memory. It then returns to you the start address of the memory block. This (and other ...
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How can a CPU be busy during DMA access with burst mode transfer

During burst mode in a DMA access, the DMAC has control over the bus for the whole transfer session which includes DATA PREPARATION time as well as DATA transfer time, after the transfer is over, the ...
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28 views

How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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Getting the flit size in a Tiled Chip Multicore Processor(TCMP) system with a mesh architecture

Consider a TCMP system with, say, a 4x4 mesh Network on Chip (NoC) where each tile has a superscalar processor. It is given that that the TCMP uses 64-bit words and the inter-router link bandwidth is ...
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How to predict the time complexity of matrix multiplication and inverse on a GPU?

Nvidia GPU can speed up the matrix manipulation greatly. I want to have a basic idea to predict the consumed time for matrix manipulation. How can I analyze the time complexity of matrix ...
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How fast can 10 integer multiplications be executed?

This is self study, but not homework. I am reviewing some slides I found online and have come across the following question. Question: If the latency of integer multiply is $3$ and the cycles/issue ...
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Does Nand Flash Type Affect the Read Latency Based on Page Content?

In general, we have these types of NAND flash cells: SLC, MLC, TLC, and QLC. Since MLC flash cells can store 2 bits, the content of the cell can be 00, 01, 10, or 11 which are detected using different ...
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Where is the register position in a CPU (real image illustration)?

I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
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1answer
54 views

How many RAW dependencies are present in these instructions?

What is the number of RAW dependencies in below set of instructions? I1: R1 = R2 - R3 I2: R2 = R1 + R3 I3: R3 = R1 + R2 I4: R1 = R2 - R2 I can see the following ...
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Can differennt computation model lead to different complexity?

There are many examples where someone replaces a CPU with a GPU or an FPGA and get a performance boost of $\times 100$ or more, but is it possible for a change in the architecture of computational ...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...

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