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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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96 votes
13 answers
26k views

What are GPUs bad at?

I understand that GPUs are generally used to do LOTS of calculations in parallel. I understand why we would want to parallelize processes in order to speed things up. However, GPUs aren't always ...
ChocolateOverflow's user avatar
80 votes
3 answers
51k views

How do computers keep track of time?

How are computers able to tell the correct time and date every time? Whenever I close the computer (shut it down) all connections and processes inside stop. How is it that when I open the computer ...
Soham's user avatar
  • 937
78 votes
9 answers
23k views

Why is addition as fast as bit-wise operations in modern processors?

I know that bit-wise operations are so fast on modern processors, because they can operate on 32 or 64 bits on parallel, so bit-wise operations take only one clock cycle. However addition is a complex ...
Teodor Dyakov's user avatar
66 votes
2 answers
31k views

What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
Ankit's user avatar
  • 1,327
59 votes
7 answers
33k views

Why does a processor have 32 registers?

I've always wondered why processors stopped at 32 registers. It's by far the fastest piece of the machine, why not just make bigger processors with more registers? Wouldn't that mean less going to the ...
Matt Capone's user avatar
58 votes
12 answers
29k views

Does a byte contain 8 bits, or 9?

I read in this assembly programming tutorial that 8 bits are used for data while 1 bit is for parity, which is then used for detecting parity error (caused by hardware fault or electrical disturbance)....
xtt's user avatar
  • 729
57 votes
11 answers
35k views

Why would anyone want CISC?

In our computer systems lecture we were introduced to the MIPS processor. It was (re)developed over the course of the term and has in fact been quite easy to understand. It uses a RISC design, that is ...
Raphael's user avatar
  • 72.5k
52 votes
10 answers
7k views

If the speed of electrical charge hasn't changed, how have computers become faster?

Everyone knows computing speed has drastically increased since their invention, and it looks set to continue. But one thing is puzzling me: if you ran an electrical current through a material today, ...
leylandski's user avatar
41 votes
6 answers
6k views

How does a computer work?

I have been a computer nerd for many many years. I can program in quite a few languages, and I can even build them. I sat down with a buddy the other day and asked how a computer actually takes ...
Christian's user avatar
  • 519
40 votes
7 answers
34k views

How does the computer determine whether a number is smaller or greater than another?

It might sound like a stupid question but I'm really curious to know how a computer knows that $1<2$? Also, how does a computer know that the order of integer is $1,2,3,4,5,\ldots$ and alphabet is ...
Ricky Stam's user avatar
38 votes
2 answers
2k views

Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...
Gilles 'SO- stop being evil''s user avatar
33 votes
2 answers
95k views

What are system clock and CPU clock; and what are their functions?

While reading a book, I came across a paragraph given below: In order to synchronize all of a computer’s operations, a system clock—a small quartz crystal located on the motherboard—is used. The ...
swdeveloper's user avatar
29 votes
6 answers
46k views

Why Do Computers Use the Binary Number System (0,1)?

Why Do Computers Use the Binary Number System (0,1)? Why don't they use Ternary Number System (0,1,2) or any other number system instead?
Rai Ammad Khan's user avatar
29 votes
6 answers
7k views

Why are reversible gates not used?

I was reading the book "The singularity is near" written by Kurzweil and he mentioned the reversible gates like for example the Fredkin gate. The advantage using such gates is that we could get rid of ...
Mehdi's user avatar
  • 443
28 votes
3 answers
8k views

Why is the Nintendo Entertainment System (NES) referred to as an 8-bit system, rather than a 1-byte system?

As far as I've understood it, referring to this system as an 8-bit system points out that one can access 8 bits of data in one instruction. While I understand that we're not saving vast amounts of ...
Alec's user avatar
  • 391
28 votes
3 answers
8k views

What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
102948239408's user avatar
27 votes
12 answers
19k views

Is a universal assembly language for all computers possible?

I would like to ask a few questions about Assembly language. My understanding is that it's very close to machine language, making it faster and more efficient. Since we have different computer ...
nTuply's user avatar
  • 469
26 votes
1 answer
4k views

Is a stack overflow detected by hardware or software?

Is it the task of the software (operating system) to detect stack overflows or is a stack overflow detected in hardware, causing an exception in the CPU?
gilianzz's user avatar
  • 581
25 votes
7 answers
17k views

Why floating point representation uses a sign bit instead of 2's complement to indicate negative numbers

Consider a fixed point representation which can be regarded as a degenerate case of a floating number. It is entirely possible to use 2's complement for negative numbers. But why is a sign bit ...
koo's user avatar
  • 351
24 votes
5 answers
346k views

How to calculate the number of tag, index and offset bits of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
compski's user avatar
  • 403
22 votes
9 answers
4k views

Would it be wrong to say that the processor (and hardware) is the implementation of an interpreter for machine language?

The question is basically in the title. I know that a computers hardware is of course some physical object, where as the interpreter is some abstract thing that does something abstract with the code ...
Quantumwhisp's user avatar
22 votes
4 answers
6k views

CPU frequency per year

I know that since ~2004, Moore's law stopped working for CPU clock speed. I'm looking for a graph showing this, but am unable to find it: most charts out there show the transistor count or the ...
peoro's user avatar
  • 323
22 votes
1 answer
20k views

Memory Consistency vs Cache Coherence

Is it true that Sequential Consistency is a stronger property than Cache Coherence? According to Sorin, Daniel J; Hill, Mark D; Wood, David A: A Primer on Memory Consistency and Cache Coherence, ...
Ayrat's user avatar
  • 1,075
21 votes
5 answers
5k views

What does machine code actually look like while being run?

When machine code is actually being executed by hardware and the CPU, what does it look like? Would it look like binary, as in instructions being represented by ones and zeros, or would it be ...
Tim Hardly's user avatar
21 votes
3 answers
1k views

Are today's massive parallel processing units able to run cellular automata efficiently?

I wonder whether the massively parallel computation units provided in graphic cards nowadays (one that is programmable in OpenCL, for example) are good enough to simulate 1D cellular automata (or ...
Stéphane Gimenez's user avatar
20 votes
3 answers
3k views

How would a CPU designed purely for functional programming be different?

CPU's are to an extent designed with in mind the software that people will write for it, implicitly or explicitly. It seems to me that if you look at the design of instruction set architectures, ...
user56834's user avatar
  • 3,892
19 votes
6 answers
3k views

How can I academically say that 'one computer is slower than the other'?

I'm writing a research paper and I have to basically say that one microcontroller is slower than an other microprocessor. However, I'm worried that simply saying that it's 'slower' wouldn't be ...
Maksimiliāns 's user avatar
19 votes
2 answers
10k views

What is a GPU year?

I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years". What is a GPU year? How long is that?
Frederic Chopin's user avatar
19 votes
2 answers
18k views

What is "memory coalescing"?

I came to know that the graphic processing unit have something called memory coalescing. On reading on it I was not clear on the topic. Is this any way related to Memory Level Parallelism. I have ...
sai kiran grandhi's user avatar
19 votes
2 answers
614 views

purpose of supercomputers

Last fall I went on a tour of the Blue Waters supercomputer at the University of Illinois. I asked whether anyone ever used the entire computer. I was told that it was always working on multiple ...
Mitchell Kaplan's user avatar
18 votes
11 answers
5k views

Why do logic gates behave the way they do?

I am a Software Developer but I came from a non-CS background so maybe it is a wrong question to ask, but I do not get why logic gates/boolean logic behave the way they do. Why for example: ...
aldokkani's user avatar
  • 317
16 votes
5 answers
21k views

Will the future quantum computers use the binary, ternary or quaternary numeral system?

Our current computers use bits, so they use the binary numeral system. But I heard that the future quantum computers will use qubits instead of simple bits. Since in the word "qubit" there is the ...
Core-Crash's user avatar
16 votes
7 answers
16k views

How is a program executed at the CPU level?

I know this is a very common question. But I have a different angle in my mind. I will just try to articulate it here. From what I know, every instruction that a CPU executes, is in machine language ...
user2827893's user avatar
16 votes
4 answers
4k views

why do CPU architectures use a flags register (advantages?)

Some CPUs have a flags register (ARM,x86,...), others don't (MIPS,...). What's the advantage of having a CMP instruction to update the flags register followed by a branch instruction instead of using ...
model world's user avatar
16 votes
1 answer
3k views

Why use SIMD if we have GPGPU?

I thought this question is better served in the CS part of Stack Exchange. Now that we have GPGPUs with languages like CUDA and OpenCL, do the multimedia SIMD extensions (SSE/AVX/NEON) still serve a ...
jonfrazen's user avatar
  • 161
15 votes
1 answer
22k views

How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
audiFanatic's user avatar
15 votes
3 answers
4k views

Logic gates from everyday materials

Logic gates are an abstract device which can be implemented with electromagnetic relays, vacuum tubes, or transistors. These implemenations have been successful in computing in part because of ...
Jason Kleban's user avatar
15 votes
2 answers
16k views

Why did MIPS include shamt and distinguish funct/opcode?

I'm confused as to why the MIPS designers would include 5 bits dedicated to shifting and have separate opcode and function bits. Because MIPS is so RISC I assume that only shifting would be done in a ...
qwr's user avatar
  • 618
14 votes
2 answers
4k views

Do computers actually use carry-lookahead adders?

There are plenty of details about carry lookahead adders such as Kogge-Stone, Lander-Fischer, etc. in college CS courses. They are described as "common in the industry". However, I can't find any ...
qwr's user avatar
  • 618
14 votes
2 answers
622 views

Organisation and Architecture of Quantum Computers

What are devices and their interconnections used alongwith Quantum Processors? Are they compatible with hardware devices like Cache, RAM, Disks of current computers?
check123's user avatar
  • 530
14 votes
3 answers
293 views

Is there an abstract machine that can capture power consumption?

When reporting algorithmic complexity of an algorithm, one assumes the underlying computations are performed on some abstract machine (e.g. RAM) that approximates a modern CPU. Such models allow us to ...
user avatar
14 votes
1 answer
419 views

Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
Juho's user avatar
  • 22.6k
14 votes
2 answers
416 views

Are CPU architectures biased towards procedural runtimes?

Are there any changes that could be made to CPUs to make them perform better for concurrent runtimes like Rust? For instance, are there changes to branch prediction implementations or cache sizes ...
paIncrease's user avatar
13 votes
3 answers
1k views

How does the processor find kernel code after an interrupt?

When an interrupt occurs, the processor preempts the current process and calls kernel code to handle the interrupt. How does the processor know where to enter the kernel? I understand that there are ...
Philipp Murry's user avatar
12 votes
2 answers
4k views

How is conditional jump implemented in the CPU?

After reading the question I'm still not sure how CPU does branching. I understand that we have an instruction counter which points to the current instruction. And after performing conditional jump it ...
LNK's user avatar
  • 239
11 votes
3 answers
5k views

Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux

I'm reading CSAPP and couldn't wrap my head around this part: Summary of what the section says: Intel Core i7 support a 48-bit virtual address space and 52-bit physical address space. Core i7 uses a ...
Nicholas Humphrey's user avatar
11 votes
5 answers
1k views

Why is the OS design able to reduce power consumption?

I have read that OSes like Android and iOS are somehow optimised to improve battery life. My understanding is that a CPU executes a certain number of operations in a certain time, so I would think ...
neelsg's user avatar
  • 221
11 votes
3 answers
4k views

CPU Cache is managed by which software component?

CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
gpuguy's user avatar
  • 1,799
11 votes
4 answers
10k views

Why do we need so many transistors in a chip, and how are they managed?

My knowledge is very vague as all we have are visual diagrams etc, but we have memory address and registers, the ALU being the heart(apparently). Single core CPUs process one instruction at a time ...
user12979's user avatar
  • 211
11 votes
3 answers
3k views

Data General MV/8000 virtues of "No mode bit"

I'm reading Tracy Kidder's "The Soul of a New Machine" where a team at Data General design a new machine (codenamed "Eagle", later named MV/8000). It is 32-bit extension of a previous architecture (...
Morty's user avatar
  • 253

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