Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How was von Neumann's architecture turned into a parallel capable architecture and is there any limitations to that?

Back when von Neumann came up with his computer architecture parallel machines and multi-core processors weren't a thing but now almost all machines have multiple cores and are able to run programs in ...
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Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?

Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years. Or the frequent changing of smartphones has a ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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What is the difference between speculative execution & branch prediction?

In computer architecture I'm confused between speculative execution & branch prediction. Are the same or different?
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Minimal number of resources such that the system is considered safe?

In a system with a single type of resource, there are 8 processes with the following maximal requirements: Process P1 P2 P3 P4 P5 P6 P7 P8 MAX 75 60 65 35 30 45 30 30 Specify the minimal value for ...
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120 views

Must a Turing machine tape be binary?

I once asked why does computer data bits are usually organized on binary (base 2) sets, rather than on unary (base 1) sets, aiming to also understand why its not also ternary (base 3), heptary (base 7)...
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Why do register machines outperform stack machines?

Wikipedia says stack machine “designs have though been routinely outperformed by the traditional register machine systems, and have remained a niche player in the market.” Why is this?
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What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
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How Can We Classify Summit Supercomputer in Terms Of Topology

Summit supercomputer has Processor: IBM POWER9 22C 3.07GHz Interconnect: Dual-rail Mellanox EDR Infiniband. So how can we classify in terms of topology? How can I find resources about this subject?
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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About Control Unit in CPU and Clock Cycle

I've been studying about CPU and I am trying to implement a small CPU, like MU0. Control unit gets instruction and generates and gives several control signals to other parts of CPU, such as ALU, PC, ...
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Why using Hyper-threading can lead to performance degradation

I have read it at various places like this, that Hyper-threading leads to performance degradation. I am unable to get why or how hyper-threading leads to degradation. Why it is so that even when Hyper-...
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Does the aliasing problem show up in a virtually indexed physically tagged cache?

Basically, and as a simple method, we can access cache with Physical Address which is from the TLB. But, as another method, we can access cache with Virtual Address. But, in this case, if the cache ...
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Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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Were boolean logic used in the analog computers?

I began a simple collection of the events behind todays computers. My knowledege in these fields is so limited, and I read: "In the 1930s and working independently, American electronic engineer ...
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Computer Architecture, Memory Interleaving. Decoding step can be interleaved?

A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ ...
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What is the theoretical minimum number of “switches” requried to implement a Turing-complete CPU?

Where "switches" are the basic abstract building blocks for logic gates: vacuum tubes, transistors, magnetic relays, or whatever. We're not counting any switches in the RAM or tape drive ...
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How are CPU architecture and word size related?

I did lot of research on internet but couldn't get my answer. I want to know what is the difference between the word size and CPU architecture? For eg.- I read that CPU of 32-bit architecture can ...
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Can a 32-bit processor work with a 64-bit size word?

In a 32-bit byte addressable memory system, each "row" has 4 bytes and each byte has a 32-bit address. My question is: can I read and/or write word of length 64 bits from/to memory? In other terms, ...
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what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
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Double Write After Write Dependency in out-of-order/in-order executions

What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register. We know we can solve a simple WAW dependency by ...
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How would I go about calculating the index field / tag field?

For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas? Given a cache that holds 512 words and block size of one word. ...
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Full adder carry expression

I'm learning about logic circuits and I've come across full adder. In the book they derived its two carry out expressions - Cout = x&&y || x&&z || y&&z and Cout = x&&...
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Cache Direct Map access confusion

Ok, I've found a good example But it doesn't really answer my question. Simple Example We have a 8 two-word blocks. So we have an offset of 1 bit. Say we have two references 33 and 32. ...
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how to calculate the speed of memory

I checked my Mac, it shows the memory is 16 GB 2400 Mhz, does it mean that the bandwidth is $ \dfrac{16\times1024}{8} \times 2400$, is there any thing wrong with that calculation, because the value ...
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Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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Do industrial automation PLCs have their own special purpose firmware or Instruction Set Architecture?

What is the ISA on the top of which the Programmable Logic Controllers run? Do they have one like in our personal computing devices having Intel x86, amd64 or ARM architecture for smartphones?
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Definitions of Computer Architecture and Computer Organization seems confusing

So there was this question in one of my class tests. It may seem very simple and straight-forward, but I am unable to catch up with its meaning or explanation. I have referred my textbook of COMPUTER ...
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Is there code below microcode?

Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
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Memory Invalidation and Misses

Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's ...
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How would I calculate the cache hit rate (ratio) percentage?

If I am correct the hit rate formula is: Hit ratio = successful hits / total requests... so would the question below be formatted as such: I tried 4 entries / 8 memory accesses but that wasn't right ...
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How to compute the Cycles in a pipelined single cycle processor

I'm an undergrad studying computer engineering and I'm in my first of many courses on computer organization/architecture. In the lectures and online I see diagrams like the one pictured below from the ...
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161 views

Pipelining and instruction cycle

Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7, R5, R6} \\ \text{...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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Types of recordings on magnetic disks

Is my searching about the types correct? Types of recordings on magnetic disks Write: The current which goes through the coil produces magnetic field and then the pulses are sent to the head which ...
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Help understanding main memory to cache block mapping

I'm currently self-learning on the cache memory and have come across a method on how to find out which cache block a memory address will be mapped to: ...
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Why return address may be lost and information in mask, processor registers may be ambiguous if an interrupt is acknowledged in following situation?

In the text Computer System Architecture (3rd Edition) by M Morris Mano , on pg. 415 under the section parallel priority interrupts I came across the following statements. The bit in the interrupt ...
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Tag storage when using HBM as an L4 cache

I'm reading through Computer Architecture: A Quantitative Approach, Sixth Edition, and I'm trying to understand the issues surrounding tag storage in using HBM as an L4 cache. The primary concern ...
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Calculating the pipeline speed up in case we have an infinite amount of stages

I have the following question: We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of ...
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Hardware implementation of direct mapped , set associative mapped and fully associative cache

I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
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How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
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If an instruction contains an address, how is it copied to the MAR?

Since the Memory address bus is unidirectional, how is an address copied to the MAR if a previous instruction such as "STO 150" contains an address? STO would store the contents of the ...
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Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
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Reference asking : High Performance Computer Architecture

Topics Pipelining: Basic concepts, instruction and arithmetic pipeline, data hazards, control hazards, and structural hazards, techniques for handling hazards. Exception handling. Pipeline ...
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Find number of platters of a given disk

I am kinda blocked trying to figure out the answer to this question. Mind helping? A manufacture wishes to design a hard disk with a capacity of 60 GB or more (using the standard definition of 1GB = ...
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Arithmetic on signed 12-bit octal number stored in sign magnitude form

What is 4365 − 3412 when these values represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal. Show your work. Octal to binary: 4365: 100 011 110 ...
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Do we need to check for mantissa overflow in floating point multiplication?

We do check for the mantisas overflow in floating point addition e.g. If we are adding $8.02 \times 10^3 + 9.01 \times 10^3 =17.03 \times 10^3$ i.e we get an overflow, so we shift the number right ...
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I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
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How does the Program Counter work?

I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction. But now my question is, how do you ...
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Loop Dependencies

Say I have loop like this, for(1 to 10) { A[i][j]=A[i][j]; } What kind of dependency is this? RAW or WAR? According to me it is none, since there is no problem ...

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