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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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31 views

Little endian architecture,

Address 0000 stores 0xde 0001 stores 0xad 0002 stores 0xbe 0003 stores 0xef Treat the data stored as 2 16 bit integers, what are the two values stored? I thought the answer would be 0xadde and 0xefbe ...
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4answers
2k views

How does a computer play a video while doing something else?

How is video playback done on a computer? It's obviously not relying purely on the CPU, since video playback continues when a user performs another activity, such as typing into a YouTube comment ...
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1answer
20 views
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2answers
47 views

What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?

I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
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0answers
24 views

Risc-V extension for dismissible loads

Certain architectures have "dismissible loads" in addition to normal loads: when the load is denied, instead of issuing an exception (leading to a segmentation fault), a default value (e.g., ...
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1answer
30 views

How does virtual memory work when it need to save data in physical memory into disk?

I'm reading a textbook which desribe VM as: a data structure stored in physical memory known as a page table that maps virtual pages to physical pages. The address translation hardware reads the page ...
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1answer
41 views

Cache Miss and Processor Speed

today in my class my professor mentioned that Cache misses becomes more expensive as the speed of the processor increases But he didn't explain the reason. I ...
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1answer
92 views

Universal Turing Machine algorithm

First, I learned this based on these facts: Turing machine (TM) will be define with 7-tuple Notation, $M=\langle Q,G,b,S,d,q_0,F\rangle$. Any computation rules that can use to simulate any possible ...
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1answer
129 views

Unsigned/signed boolean

Answer is c). I understand that the expression evaluates to true but what does signed/unsigned have to do with booleans?
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0answers
16 views

Is there any research on allocating memory across multiple non-contiguous regions?

From my understanding, malloc and-the-like allocate contiguous blocks of memory. It then returns to you the start address of the memory block. This (and other ...
2
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1answer
53 views

Course teaching time complexities in real life systems

Having mis-read What course in CS deals with the study of RAM, CPU, Storage? I now wonder what course in CS deals with time and space complexities including GPUs, CPU caches in multiple levels, seek ...
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1answer
60 views

Vectorization vs Asynchronous parallelism

I have taken a course "Programming for Performance" in my college and in the first week of the course, I have come across vectorization and Asynchronous Parallelism. But I am unable to ...
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2answers
45 views

Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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0answers
27 views

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh ...
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2answers
881 views

How to improve the CPI and Speed up factor in CPU-OS simulator?

I am using the CPU-OS simulator by Besim Mustafa(https://www.merlot.org/merlot/viewMaterial.htm?id=476196) and I am studying Pipeline Stages. I have written a simple program and captured the metrics ...
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1answer
851 views

Booth's algorithm Question : Binary Number Arithmetic (Multiplication)

It's being said booth's algorithm produces the output exactly as normal binary multiplication while reducing the number of operations performed and can be used for both positive and negative numbers ! ...
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2answers
100 views

How is CPU different from GPU?

A central processing unit offers to handle various operations like calculating, watching movies, making presentation etc. While a graphics processing unit is majorly used for the purpose of video ...
2
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3answers
142 views

Do the newest computers still have ROM?

Now that many computers use UEFI instead of BIOS to boot the computer, and UEFI instructions are usually stored in a hidden hard disk partition, does this mean the newest computers do not need to have ...
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0answers
9 views

Data Hazards and stalls

I am studying for my exam tomorrow and I am having difficulty in the below code : sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Due ...
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0answers
43 views

ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
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0answers
45 views

How can a CPU be busy during DMA access with burst mode transfer

During burst mode in a DMA access, the DMAC has control over the bus for the whole transfer session which includes DATA PREPARATION time as well as DATA transfer time, after the transfer is over, the ...
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2answers
65 views

Communication between hardware components

We know that each component has different frequencies, but what happens when a fast component directly comunicates with a slow one?
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1answer
80 views

How does computer memory store the file name?

I have this doubt for long time. When i save a notepad file, it takes the memory for the information in the file. let's say, I type 'ABC' in notepad and saved the filename as stack, it shows that the ...
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2answers
356 views

If the MOVE instruction in a Transport Triggered Architecture can implement a NAND gate (as a Functional Unit)

Background I'm looking at Transport Triggered Architectures (also this), linked to from an OISC page listing many different 1-Instruction Set Computers. It basically says the following: TTA ...
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1answer
108 views

How much space an ascii character really takes on a 64 bit word addressable memory?

I know that an ASCII character needs 1 byte of memory for storage, but if a computer uses a 64-bit word addressable memory does it mean that the character actually takes 8 bytes even when only 1 byte ...
2
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0answers
50 views

Confused with an Instruction Cycle question

Here's the question The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
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2answers
794 views

why are WAW and WAR hazards not possible in mips architecture

i have read about data hazards and then came across that mips architecture doesn't allow WAR AND WAW hazards can someone please help me understand it? the reason is not given in the book the MIPS ...
1
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1answer
94 views

How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
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0answers
23 views

What bus DIMM (RAM module) uses?

I know there are different types of BUS like PCI, SCSI, ISA etc. What specific type of bus (for address bus and data bus) do a DIMM module use ?
2
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2answers
121 views

How is Memory Segmentation done in 8086?

Basically what I know is that 8086 can address up to 1 MB of locations which are divided in 4 segments(code, data, extra and stack) 64 KB each. But 64 KB * 4 is 256 KB, which doesn't add up to 1 MB(...
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0answers
28 views

How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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0answers
34 views

How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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3answers
122 views

Transport Triggered CPU Architecture MOV and Turing Completeness

Reading up on TTA CPU designs and the wikipedia article states that Some TTA implementations support conditional execution. The trick to make an TTA ISA Turing-complete with an unconditional MOV ...
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0answers
219 views

What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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0answers
12 views

Cache Blocks Direct Mapping

If the main memory address has 18 bits (7 for tag,7 for line and 4 for word) and each word is 8 bits. I found that the main memory capacity is 256-KBytes, total cache lines is 128 line, total cache ...
2
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0answers
14 views

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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2answers
149 views

Big-endian systems and the smallest memory address

I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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1answer
56 views

Functions of CPU

What part of the CPU communicates with all the other parts of the processor and makes the processor faster by containing frequently used data or instructions?
2
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3answers
733 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
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2answers
796 views

Does the Hack computer from “The Elements of Computing Systems” use Von Neumann architecture?

I'm reading "The Elements of Computing Systems" (subtitled "Building a Modern Computer from First Principles - Nand to Tetris Companion) by Noam Nisan and Shimon Schocken. Chapter 4 is about machine ...
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0answers
63 views

direct-mapped cache

problem is as follow: For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits) Tag: 63-10 Index: 9-5 Offset: 4-0 I ...
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0answers
7 views

Getting the flit size in a Tiled Chip Multicore Processor(TCMP) system with a mesh architecture

Consider a TCMP system with, say, a 4x4 mesh Network on Chip (NoC) where each tile has a superscalar processor. It is given that that the TCMP uses 64-bit words and the inter-router link bandwidth is ...
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2answers
63 views

Confusion about “false sharing”

This is a homework problem that I have In a multicore system, you are running the code on the right on each core, and it suffers from false sharing. You can assume ...
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3answers
956 views

Where should I start to understand how computers work? [duplicate]

I am interested in how computers work but I have no idea how the concept of 0's and 1's converts to making possible for people to control a computer by programming. I would like to understand from ...
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1answer
346 views

Assembly decision loops

An high level language such as C has many statements for decision and loops while an assembly such the MIPS' one has few. With slt, ...
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1answer
30 views

Procedure for finding if Overflow occurs on addition

I have two 4-bit 2's complement numbers a,b, and their sum in s (Also a 4-bit 2's complement number). Using only the basic logical operations, I need to write a procedure to find if an overflow occurs....
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1answer
97 views

Computing average access time

A computer has a cache memory and a main memory with the following features: - Memory cache access time: 4 ns - Main memory access time: 80 ns - The time ...
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2answers
4k views

SCAN and CSCAN algorithms of disk scheduling

I am having hard time understanding the working of SCAN and CSCAN algorithm of disk scheduling.I understood FCFS,Closest Cylinder Next but heard that SCAN resembles elevator mechanism and got confused....
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1answer
102 views

Binary to ASCII using logical operations

I am learning Computer Architecture from Introduction to Computing Systems (2nd Edition) and am stuck on this question. What operations can be used to convert the binary representation of 3 into ...
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0answers
23 views

Finding the timestamps of processes implementing Lamport's clocks

I have been asked this question, but don't know how to go about answering it. Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...

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