Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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4
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2answers
1k views

Time units required for Interrupt Cycle

I am reading William Stallings Computer Organization & Architecture to understand about control unit & micro-operations. Stallings explain that interrupt cycle requires 3 time units to ...
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3answers
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CPU Cache is managed by which software component?

CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
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Mean time to failure calculation help [duplicate]

Given this formula how do you calculate the following? I don't understand, can some one explain? ...
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2answers
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What is the system's mean time to failure?

I have the following homework problem: A 10 TB disk drive has an MTTF of 6,000,000 hours. How much data can we store in a system comprised of these disks, if we want the system MTTF to be at least 1....
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The amount of ROM needed to implement a 4-bit multiplier?

For a 4-bit multiplier there are $2^4 \cdot 2^4 = 2^8$ combinations. The output of 4-bit multiplication is 8 bits, so the amount of ROM needed is $2^8 \cdot 8 = 2048$ bits. Why is that? Why does ...
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4answers
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Does the write through cache copies the whole block or just the byte which is updated?

Just a basic question to ask Does the write through cache copies the whole block or just the byte which is updated? I went through the following question Array A contains 256 elements of 4 bytes ...
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1answer
900 views

Where do these DRAM row/column calculations come from?

Let r be the number of rows in a DRAM array, and c be the number of columns. Apparently, DRAM with organization 16x1 requires least pins when r = c = 4 because fewer address bits are required to ...
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2answers
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Theoretical minimum number of registers for a modern computer?

I took a course on compilers in my undergraduate studies in which we wrote a compiler that compiles source programs in a toy Java-like language to a toy assembly language (for which we had an ...
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1answer
531 views

categories of registers and and storage in them

The Wikipedia article on processor registers mentions: Address registers hold addresses and are used by instructions that indirectly access primary memory. Which addresses does this sentence refer ...
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7answers
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How does the computer determine whether a number is smaller or greater than another?

It might sound like a stupid question but I'm really curious to know how a computer knows that $1<2$? Also, how does a computer know that the order of integer is $1,2,3,4,5,\ldots$ and alphabet is ...
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2answers
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Doubt regarding cache hit ratios and access time

Question 1: What is the average access time for a 3-level memory system with access time $T_1$, $2T_1$ and $3T_1$? (Hit ratio $h_1$ = $h_2$ = 0.9) The solution given is: $0.9[T_1] + 0.1(0.9[2*T_1] + ...
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2answers
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Mathematical model on which current computers are built

It is said that "The Turing machine is not intended as practical computing technology, but rather as a hypothetical device representing a computing machine. Turing machines help computer scientists ...
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Commonly used Error Correcting Codes

We know error correcting codes are parameterized as (n,k,d) codes. I wanted to know the values of these parameters for some commonly used error correcting codes in computer memories or in DRAMs, etc. ...
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1answer
196 views

How do you go about designing a vector processor architecture for the sum of matrix products?

The following equation is a matrix expression where $B_i$ and $C_i^T$ are $n\times n$ matrices and k is a positive integer: $$P = \sum_{i=1}^k B_i C_i^T $$ So $P = B_1 C_1^T + B_2 C_2^T + \cdots +...
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1answer
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Using Amdahl's law how do you determine execution time after an improvement?

Speeding up a new floating-point unit by 2 slows down data cache accesses by a factor of 2/3 (or a 1.5 slowdown for data caches). If old FP unit took 20% of program's execution time and data cache ...
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1answer
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How to convert process / cpu core based upon MIPS?

I want to know how can i find number of cpu cores/processor supported given i have the MIPS value? For e.g I want to know the number of matching cores/processor to process speed of 18 triilion ...
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7answers
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Why floating point representation uses a sign bit instead of 2's complement to indicate negative numbers

Consider a fixed point representation which can be regarded as a degenerate case of a floating number. It is entirely possible to use 2's complement for negative numbers. But why is a sign bit ...
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1answer
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Indirection in IAS computer

From Computer Organisation and Architecture: The IAS operates by repetitively performing an instruction cycle. Each instruction cycle consists of two sub cycles. During a fetch cycle, the ...
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1answer
150 views

Could I simulate the implementation of memory components

I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu. In the paper ...
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6answers
5k views

How does a computer work?

I have been a computer nerd for many many years. I can program in quite a few languages, and I can even build them. I sat down with a buddy the other day and asked how a computer actually takes ...
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1answer
514 views

Why can L3 caches hold only shared blocks?

In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches (e....
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2answers
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Theoretical speed gain of quad core vs. single core

I first asked this question at cstheory, but they suggested to ask my question here, so here it goes ... I'm working on my masters thesis and I need to have theoretical value of the (average) speed ...
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7answers
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Ternary processing instead of Binary

Most of the computers available today are designed to work with binary system. It comes from the fact that information comes in two natural form, true or false. We humans accept another form of ...
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1answer
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When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different ...
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1answer
256 views

What techniques exist for energy-efficient computing and networking?

I am currently reviewing the potentials of cloud computing regarding energy efficiency and green IT. In connection with this review I am having a look on techniques for increasing energy-efficiency in ...
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2answers
529 views

Organisation and Architecture of Quantum Computers

What are devices and their interconnections used alongwith Quantum Processors? Are they compatible with hardware devices like Cache, RAM, Disks of current computers?
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2answers
664 views

Big-Endian/Little-Endian argument - paper by Danny Cohen

Reading a book I was redirected to "On holy wars and a plea for peace" paper by Danny Cohen, which covers the "holy war" between big-endians and little-endians considering byte-order. Reaching the ...
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4answers
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What is meant by interrupts in the context of operating systems?

I've decided to read Operating Systems Concepts by Silberschatz, Galvin Gagne (8th edition) over the summer. I've gotten to a topic that's confusing me - interrupts and their role as it relates to ...
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1answer
342 views

Frame Pointers in Assembler

I am currently learning assembly programming on wombat 4, I am looking at Frame pointers. I understand exactly what a frame pointer is: it is a register and are used to access parameters on a stack. ...
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1answer
133 views

Requirements for emulation

What are the complete specifications that must be documented in order to ensure the correct execution of a particular program written in Java? For instance, if one were archiving a program for long-...
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2answers
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What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
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3answers
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Logic gates from everyday materials

Logic gates are an abstract device which can be implemented with electromagnetic relays, vacuum tubes, or transistors. These implemenations have been successful in computing in part because of ...
14
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1answer
378 views

Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
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4answers
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CPU frequency per year

I know that since ~2004, Moore's law stopped working for CPU clock speed. I'm looking for a graph showing this, but am unable to find it: most charts out there show the transistor count or the ...
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2answers
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Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...
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3answers
269 views

Is there an abstract machine that can capture power consumption?

When reporting algorithmic complexity of an algorithm, one assumes the underlying computations are performed on some abstract machine (e.g. RAM) that approximates a modern CPU. Such models allow us to ...
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11answers
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Why would anyone want CISC?

In our computer systems lecture we were introduced to the MIPS processor. It was (re)developed over the course of the term and has in fact been quite easy to understand. It uses a RISC design, that is ...
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3answers
991 views

Are today's massive parallel processing units able to run cellular automata efficiently?

I wonder whether the massively parallel computation units provided in graphic cards nowadays (one that is programmable in OpenCL, for example) are good enough to simulate 1D cellular automata (or ...
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2answers
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Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather ...

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