Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How to convert process / cpu core based upon MIPS?

I want to know how can i find number of cpu cores/processor supported given i have the MIPS value? For e.g I want to know the number of matching cores/processor to process speed of 18 triilion ...
asadz's user avatar
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24 votes
7 answers

Why floating point representation uses a sign bit instead of 2's complement to indicate negative numbers

Consider a fixed point representation which can be regarded as a degenerate case of a floating number. It is entirely possible to use 2's complement for negative numbers. But why is a sign bit ...
koo's user avatar
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Indirection in IAS computer

From Computer Organisation and Architecture: The IAS operates by repetitively performing an instruction cycle. Each instruction cycle consists of two sub cycles. During a fetch cycle, the ...
lwm1's user avatar
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3 votes
1 answer

Could I simulate the implementation of memory components

I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu. In the paper ...
EAGER_STUDENT's user avatar
42 votes
6 answers

How does a computer work?

I have been a computer nerd for many many years. I can program in quite a few languages, and I can even build them. I sat down with a buddy the other day and asked how a computer actually takes ...
Christian's user avatar
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6 votes
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Why can L3 caches hold only shared blocks?

In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches (e....
Raphael's user avatar
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4 votes
2 answers

Theoretical speed gain of quad core vs. single core

I first asked this question at cstheory, but they suggested to ask my question here, so here it goes ... I'm working on my masters thesis and I need to have theoretical value of the (average) speed ...
EsTeGe's user avatar
  • 141
5 votes
7 answers

Ternary processing instead of Binary

Most of the computers available today are designed to work with binary system. It comes from the fact that information comes in two natural form, true or false. We humans accept another form of ...
Mert Akcakaya's user avatar
8 votes
1 answer

When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different ...
Matt's user avatar
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7 votes
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What techniques exist for energy-efficient computing and networking?

I am currently reviewing the potentials of cloud computing regarding energy efficiency and green IT. In connection with this review I am having a look on techniques for increasing energy-efficiency in ...
Erik's user avatar
  • 171
14 votes
2 answers

Organisation and Architecture of Quantum Computers

What are devices and their interconnections used alongwith Quantum Processors? Are they compatible with hardware devices like Cache, RAM, Disks of current computers?
check123's user avatar
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4 votes
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Big-Endian/Little-Endian argument - paper by Danny Cohen

Reading a book I was redirected to "On holy wars and a plea for peace" paper by Danny Cohen, which covers the "holy war" between big-endians and little-endians considering byte-order. Reaching the ...
Sim's user avatar
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What is meant by interrupts in the context of operating systems?

I've decided to read Operating Systems Concepts by Silberschatz, Galvin Gagne (8th edition) over the summer. I've gotten to a topic that's confusing me - interrupts and their role as it relates to ...
Ockham's user avatar
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5 votes
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Frame Pointers in Assembler

I am currently learning assembly programming on wombat 4, I am looking at Frame pointers. I understand exactly what a frame pointer is: it is a register and are used to access parameters on a stack. ...
Xabi's user avatar
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4 votes
1 answer

Requirements for emulation

What are the complete specifications that must be documented in order to ensure the correct execution of a particular program written in Java? For instance, if one were archiving a program for long-...
Micah Beck's user avatar
66 votes
2 answers

What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
Ankit's user avatar
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15 votes
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Logic gates from everyday materials

Logic gates are an abstract device which can be implemented with electromagnetic relays, vacuum tubes, or transistors. These implemenations have been successful in computing in part because of ...
Jason Kleban's user avatar
14 votes
1 answer

Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
Juho's user avatar
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22 votes
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CPU frequency per year

I know that since ~2004, Moore's law stopped working for CPU clock speed. I'm looking for a graph showing this, but am unable to find it: most charts out there show the transistor count or the ...
peoro's user avatar
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38 votes
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Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...
Gilles 'SO- stop being evil''s user avatar
14 votes
3 answers

Is there an abstract machine that can capture power consumption?

When reporting algorithmic complexity of an algorithm, one assumes the underlying computations are performed on some abstract machine (e.g. RAM) that approximates a modern CPU. Such models allow us to ...
user avatar
57 votes
11 answers

Why would anyone want CISC?

In our computer systems lecture we were introduced to the MIPS processor. It was (re)developed over the course of the term and has in fact been quite easy to understand. It uses a RISC design, that is ...
Raphael's user avatar
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21 votes
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Are today's massive parallel processing units able to run cellular automata efficiently?

I wonder whether the massively parallel computation units provided in graphic cards nowadays (one that is programmable in OpenCL, for example) are good enough to simulate 1D cellular automata (or ...
Stéphane Gimenez's user avatar
11 votes
2 answers

Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather ...
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