Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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How Can We Classify Summit Supercomputer in Terms Of Topology

Summit supercomputer has Processor: IBM POWER9 22C 3.07GHz Interconnect: Dual-rail Mellanox EDR Infiniband. So how can we classify in terms of topology? How can I find resources about this subject?
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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203 views

What is the difference between speculative execution & branch prediction?

In computer architecture I'm confused between speculative execution & branch prediction. Are the same or different?
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What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
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How are programs split up into pages in Memory Paging?

I am a bit confused about how the logical addresses are generated in a paging memory architecture and where and when a program is split up into pages. I understand how logical addresses are translated ...
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Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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Were boolean logic used in the analog computers?

I began a simple collection of the events behind todays computers. My knowledege in these fields is so limited, and I read: "In the 1930s and working independently, American electronic engineer ...
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1answer
98 views

What is the theoretical minimum number of "switches" requried to implement a Turing-complete CPU?

Where "switches" are the basic abstract building blocks for logic gates: vacuum tubes, transistors, magnetic relays, or whatever. We're not counting any switches in the RAM or tape drive ...
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What is a cache write miss?

I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393; The other key ...
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how to calculate the speed of memory

I checked my Mac, it shows the memory is 16 GB 2400 Mhz, does it mean that the bandwidth is $ \dfrac{16\times1024}{8} \times 2400$, is there any thing wrong with that calculation, because the value ...
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105 views

Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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Memory Invalidation and Misses

Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's ...
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Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?

Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years. Or the frequent changing of smartphones has a ...
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How would I go about calculating the index field / tag field?

For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas? Given a cache that holds 512 words and block size of one word. ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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2answers
123 views

Harvard processor structure

In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
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Why did Apple include dedicated a neural network "processor" in standard consumer products?

Not sure if this is the right place, but I guess it is better than Reddit and I couldn't find any discussion. I was wondering why Apple include a neural network "processor" and can't help ...
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329 views

Definitions of Computer Architecture and Computer Organization seems confusing

So there was this question in one of my class tests. It may seem very simple and straight-forward, but I am unable to catch up with its meaning or explanation. I have referred my textbook of COMPUTER ...
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356 views

What does "associative" exactly mean in "n-way set-associative cache"?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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421 views

Calculating the pipeline speed up in case we have an infinite amount of stages

I have the following question: We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of ...
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181 views

Is there code below microcode?

Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
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Reference asking : High Performance Computer Architecture

Topics Pipelining: Basic concepts, instruction and arithmetic pipeline, data hazards, control hazards, and structural hazards, techniques for handling hazards. Exception handling. Pipeline ...
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Is it possible to transmit bits digitally?

I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
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558 views

Find number of platters of a given disk

I am kinda blocked trying to figure out the answer to this question. Mind helping? A manufacture wishes to design a hard disk with a capacity of 60 GB or more (using the standard definition of 1GB = ...
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656 views

Arithmetic on signed 12-bit octal number stored in sign magnitude form

What is 4365 − 3412 when these values represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal. Show your work. Octal to binary: 4365: 100 011 110 ...
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I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
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46 views

Multiple correct answers for compilation

When you are asked to hand compile into assembly language, are there multiple correct answers? For example, in https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-...
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Linear Speedup and Amdahl's law

I'm having trouble understanding and solving the problem. Suppose we have a program which is composed of 3 portions A, B and C and that each portion takes $t_A$, $t_B$ and $t_C$ respectively to run on ...
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Little endian architecture,

Address 0000 stores 0xde 0001 stores 0xad 0002 stores 0xbe 0003 stores 0xef Treat the data stored as 2 16 bit integers, what are the two values stored? I thought the answer would be 0xadde and 0xefbe ...
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How would I answer this? I recently started doing computer studies at school

is this format okay? this is my first time using stackexchange.
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Why cannot Operand forwarding remove all RAW hazards?

I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
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What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?

I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
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57 views

How does virtual memory work when it need to save data in physical memory into disk?

I'm reading a textbook which desribe VM as: a data structure stored in physical memory known as a page table that maps virtual pages to physical pages. The address translation hardware reads the page ...
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Cache Miss and Processor Speed

today in my class my professor mentioned that Cache misses becomes more expensive as the speed of the processor increases But he didn't explain the reason. I ...
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Unsigned/signed boolean

Answer is c). I understand that the expression evaluates to true but what does signed/unsigned have to do with booleans?
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Is there any research on allocating memory across multiple non-contiguous regions?

From my understanding, malloc and-the-like allocate contiguous blocks of memory. It then returns to you the start address of the memory block. This (and other ...
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1answer
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Course teaching time complexities in real life systems

Having mis-read What course in CS deals with the study of RAM, CPU, Storage? I now wonder what course in CS deals with time and space complexities including GPUs, CPU caches in multiple levels, seek ...
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374 views

Is machine epsilon the largest relative error in representing a number as a floating point number?

Is machine epsilon the largest relative error in representing a number as a floating point number? There are so many definitions of machine epsilon. I'm starting to get confused. Isn't the machine ...
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102 views

Vectorization vs Asynchronous parallelism

I have taken a course "Programming for Performance" in my college and in the first week of the course, I have come across vectorization and Asynchronous Parallelism. But I am unable to ...
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Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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785 views

How is a program stored before compiling?

When we write code, after compilation the code will be converted to machine language and then stored in the hard disk. But before compiling the code, it is still in the high-level language. How and ...
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Booth's algorithm Question : Binary Number Arithmetic (Multiplication)

It's being said booth's algorithm produces the output exactly as normal binary multiplication while reducing the number of operations performed and can be used for both positive and negative numbers ! ...
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How can I mathematically show the largest possible value of a 64-bit double?

I'm a physics student wondering how I can mathematically show the largest possible value of a 64-bit double. I don't want to know just the answer, since that is freely available. The equation I was ...
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475 views

Do the newest computers still have ROM?

Now that many computers use UEFI instead of BIOS to boot the computer, and UEFI instructions are usually stored in a hidden hard disk partition, does this mean the newest computers do not need to have ...
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ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
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How can a CPU be busy during DMA access with burst mode transfer

During burst mode in a DMA access, the DMAC has control over the bus for the whole transfer session which includes DATA PREPARATION time as well as DATA transfer time, after the transfer is over, the ...
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Communication between hardware components

We know that each component has different frequencies, but what happens when a fast component directly comunicates with a slow one?
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Universal Turing Machine algorithm

First, I learned this based on these facts: Turing machine (TM) will be define with 7-tuple Notation, $M=\langle Q,G,b,S,d,q_0,F\rangle$. Any computation rules that can use to simulate any possible ...

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