Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
1,085
questions
0
votes
2
answers
211
views
When the stall is actually going to happen?
Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
- 1
1
vote
0
answers
50
views
Can old hardware be practically useful for CS problems of modern day?
Thinking about specific settings on WorldBuilding.SE, it turns out I need help from people who are more in touch with CS and Clusters. For those who curious about how it started, backstory here, ...
- 111
3
votes
3
answers
431
views
Can x86 Instruction Set be changed with microcode update?
How I understand microcode translate an instruction to microinstructions. And CPU has a unit that stores all possible of microinstructions. These microinstructions can be changed, because it load ...
- 33
1
vote
1
answer
119
views
How does a computer direct the processing of information
So I'm reading Introduction to computing systems:From bits and gates to C and beyond, and the author states that a CPU is the mechanism that
...directs the processing of information. Which is ...
- 13
2
votes
1
answer
211
views
Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?
A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
1
vote
1
answer
142
views
What is combinational circuit?
I'm reading the Digital Design and Computer Architecture by David Harris, Sarah Harris. The authors give the following definition of combinational logic:
A combinational circuit’s outputs depend only ...
- 217
1
vote
1
answer
126
views
How do I compute the power consumption of a DRAM refresh?
Given a DRAM-based memory system with a total capacity of $x$ bytes, $y$ DRAM rows and a refresh time of $t$ milliseconds, how do I compute the power consumption for one DRAM refresh? I couldn't find ...
- 19
0
votes
0
answers
109
views
Can a single core processor be MIMD?
I was wondering for if a single core processor can be MIMD? or MISD? or SIMD?
I thought MIMD's requirement is multicore, but I am not sure about this
0
votes
1
answer
117
views
When can a deterministic finite-state-automaton (DFSA) along with its input sequence be said to be a part of another DFSA?
For a Finite State Automaton / Finite State Machine (FSM) $F$, that has an input alphabet, a set of possible states, an initial state, a set of possible final states and a state transition function, ...
- 389
0
votes
1
answer
80
views
Interesting Speedup & Amdahl's law problem
I have found a problem on my Computer Architecture textbook which I have some issues with:
We have a process which spends its time in the following way:
50% of the time, it executes common ...
- 239
6
votes
2
answers
393
views
How do computers *really* work? (at the most basic level)
While learning about computers I will read about RAM and Storage and the CPU, and while these explain the architecture of a computer and how parts of a computer work together, I still don't understand ...
- 63
0
votes
1
answer
29
views
About the connection of pipelined execution and latency
Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor.
We do assume that ...
- 161
0
votes
1
answer
67
views
What will a given CPU architecture do in the event that we were to invert all of the instruction bits to a given instruction?
Given an arbitrary CPU - Architecture and its instruction set... What would be the outcome of the given inverted instruction within that Architect?
For simplicity, let's use an 8-bit CPU architecture ...
- 131
2
votes
6
answers
2k
views
Representation of unsigned integer on a little endian, big endian computer
This is a GATE 2021 exam question.
If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices ...
1
vote
0
answers
18
views
K-Map Reduction Grouping Question
I have a simple question regarding reduction using K-Maps.
My professor gave this example:
While I somewhat understand that we can only group quantities of base 2 numbers, why did my professor group ...
- 11
0
votes
0
answers
723
views
How to do -8 x -8 in a 4 bit booth multiplier?
In the general case of an n bit booth multiplier, the maximum negative value is -2n-1. So with 4 bits we can represent -8 x -8 (M=1000, Q=1000). Now if we follow Booth's algorithm for multiplying n-...
2
votes
2
answers
105
views
Which has optimum performance? raw core or multithreaded
Let's say there's a single process performed in the machine which utilizes all available processors (whether physical or logical processors). The process use 100% processor utilization most of the ...
- 123
0
votes
2
answers
757
views
How does Instruction Set Architecture (ISA) affect performance?
If 2 CPUs have the same Instruction Set Architecture, which of the following properties will be the same?
Clock Rate
CPI
Execution time
No. of instructions
MIPS
- 111
1
vote
1
answer
902
views
Formula to see where a memory address can be depicted in cache?
I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
- 211
0
votes
1
answer
80
views
How do I compute the address of the next element?
I have to work on something , but I am making an error that I can not identify. Propably, it is going to sound simple to you but it's my first course on computer architecture and there is nothing in ...
- 211
0
votes
1
answer
1k
views
Metrics on which Clock Cycles Per Instruction(CPI) depends
In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this:
The term clock cycles per instruction, which is ...
- 147
1
vote
1
answer
597
views
Must a Turing machine tape be binary?
I once asked why does computer data bits are usually organized on binary (base 2) sets, rather than on unary (base 1) sets, aiming to also understand why its not also ternary (base 3), heptary (base 7)...
- 25
0
votes
0
answers
87
views
Minimal number of resources such that the system is considered safe?
In a system with a single type of resource, there are 8 processes with the following maximal requirements:
Process
P1
P2
P3
P4
P5
P6
P7
P8
MAX
75
60
65
35
30
45
30
30
Specify the minimal value for ...
0
votes
2
answers
188
views
Why do register machines outperform stack machines?
Wikipedia says stack machine “designs have though been routinely outperformed by the traditional register machine systems, and have remained a niche player in the market.” Why is this?
0
votes
1
answer
104
views
Query Regarding Direct cache mapping [closed]
Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
- 219
1
vote
1
answer
614
views
What is the difference between speculative execution & branch prediction?
In computer architecture I'm confused between speculative execution & branch prediction. Are the same or different?
- 111
3
votes
1
answer
93
views
What's the average number of transistor switches needed to do an N-bit x N-bit multiply?
I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
- 41
2
votes
2
answers
515
views
How are programs split up into pages in Memory Paging?
I am a bit confused about how the logical addresses are generated in a paging memory architecture and where and when a program is split up into pages.
I understand how logical addresses are translated ...
- 58
1
vote
1
answer
106
views
Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?
I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
1
vote
0
answers
89
views
Were boolean logic used in the analog computers?
I began a simple collection of the events behind todays computers. My knowledege in these fields is so limited, and I read:
"In the 1930s and working independently, American electronic engineer ...
1
vote
1
answer
202
views
What is the theoretical minimum number of "switches" requried to implement a Turing-complete CPU?
Where "switches" are the basic abstract building blocks for logic gates: vacuum tubes, transistors, magnetic relays, or whatever. We're not counting any switches in the RAM or tape drive ...
- 111
3
votes
7
answers
8k
views
What is a cache write miss?
I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393;
The other key ...
- 169
0
votes
0
answers
34
views
how to calculate the speed of memory
I checked my Mac, it shows the memory is 16 GB 2400 Mhz, does it mean that the bandwidth is $ \dfrac{16\times1024}{8} \times 2400$, is there any thing wrong with that calculation, because the value ...
- 1
3
votes
1
answer
192
views
Under which conditions a given program is deterministic on x86_64 machines?
Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
user82256
0
votes
1
answer
40
views
Memory Invalidation and Misses
Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's ...
- 1,180
1
vote
1
answer
78
views
Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?
Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years.
Or the frequent changing of smartphones has a ...
- 113
-1
votes
1
answer
62
views
How would I go about calculating the index field / tag field?
For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas?
Given a cache that holds 512 words and block size of one word. ...
- 1
1
vote
0
answers
270
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 1,052
1
vote
1
answer
741
views
Two Vs Dual Port RAM
Regarding the difference between Two Vs Dual Port RAM Here is what I understand:
The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
- 11
1
vote
2
answers
180
views
Harvard processor structure
In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can ...
- 11
0
votes
2
answers
83
views
Why did Apple include dedicated a neural network "processor" in standard consumer products?
Not sure if this is the right place, but I guess it is better than Reddit and I couldn't find any discussion.
I was wondering why Apple include a neural network "processor" and can't help ...
- 1
1
vote
1
answer
541
views
Definitions of Computer Architecture and Computer Organization seems confusing
So there was this question in one of my class tests. It may seem very simple and straight-forward, but I am unable to catch up with its meaning or explanation. I have referred my textbook of COMPUTER ...
- 111
2
votes
1
answer
2k
views
What does "associative" exactly mean in "n-way set-associative cache"?
I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
- 151
-1
votes
1
answer
913
views
Calculating the pipeline speed up in case we have an infinite amount of stages
I have the following question:
We begin with a computer implemented in single-cycle implementation.
When the stages are split by functionality, the stages do not require
exactly the same amount of ...
- 123
2
votes
1
answer
292
views
Is there code below microcode?
Which is the lowest level of code (human written instruction for computers) in computer architecture? After doing minor research, I have come to the conclusion that, as far as determining a hierarchy ...
- 591
0
votes
1
answer
135
views
Reference asking : High Performance Computer Architecture
Topics
Pipelining: Basic concepts, instruction and arithmetic pipeline, data hazards, control
hazards, and structural hazards, techniques for handling hazards. Exception handling.
Pipeline ...
- 157
0
votes
4
answers
174
views
Is it possible to transmit bits digitally?
I have learnt that all data transmission is analog. Is there any mediums that could transmit bits digitally?
- 21
-2
votes
1
answer
996
views
Find number of platters of a given disk
I am kinda blocked trying to figure out the answer to this question. Mind helping?
A manufacture wishes to design a hard disk with a capacity of 60 GB or more (using the standard definition of 1GB = ...
- 1
1
vote
1
answer
2k
views
Arithmetic on signed 12-bit octal number stored in sign magnitude form
What is 4365 − 3412 when these values represent signed 12-bit
octal numbers stored in sign-magnitude format? The result should be written in
octal. Show your work.
Octal to binary:
4365: 100 011 110 ...
- 147
0
votes
0
answers
105
views
I'm to calculate the tag, index and offset for a given setup
Total Memory size = 65,536 bytes
Number of cache blocks = 32 cache blocks
Cache size = total 512 bytes
So using this info provided I cannot figure out how to calculate the cache block number.
I know ...
