Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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47 views

What happens with register usage in deeply nested functions calls (in theory)?

I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
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186 views

How many registers does a computer *need*?

I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
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How does a CPU differentiate between 1-operand instructions and 2-operand instructions?

Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction ...
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Compiler optimization which does an SMT-like optimization in software?

Say I had two functions called one after the other: ...
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3answers
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Is the constant pi (not Raspberry) ever used in general computer science?

Is the constant pi (not Raspberry) ever used in general computer science? If so, how so or when is it applicable?
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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78 views

Little Endian vs Big Endian?

Suppose a processor uses the big endian representation and x is a 32-bit integer stored in memory starting at the memory address 1000. The memory is byte-addressable, each location holding a byte. ...
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476 views

Read and write ports in a register file?

How many read and write ports in a register file? Moreover, what is the difference between a register and a register file?
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1answer
417 views

What is memory model in computer organization?

I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking ...
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Relation between CPU cycle and Addressing modes

Professor has given this question in exam. I am not able to find relevant reference for this question Which Addressing Modes (for x86 architecture) consumes more CPU cycle?(Consider all are special ...
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526 views

What are the smallest and biggest negative floating point numbers in IEEE 754 32 bit?

I am stuck with a question that asks for smallest and biggest negative floating point numbers in IEEE 754 32-bit (their representation and decimal numerical value from which one can approximate the ...
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1answer
36 views

Can a new company make a processor compatible with Windows and current software? [closed]

Would anyone apart from Intel and AMD ever be able to make a processor that can be used on a personal computer, or is it impossible? I believe it is due to them owning the x86 instruction set, which ...
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Is 'the bombe' technically a computer?what is technically meant to be a computer?

Some say that 'the bombe' created by Alan Turing is technically not a computer despite decrypting the codes. Why is it so? Is 'the bombe' technically a computer? First of all what is technically ...
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What is a GPU year?

I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years". What is a GPU year? How long is that?
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What is a sticky bit in computer architecture?

I am reading about a counter implementation in RISC Architecture. The specification reads, Sticky overflow bit is set when the counter wraps through zero. I can infer that the overflow bit is ...
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1answer
93 views

Lack of Stack Pointer Register

Suppose a processor lacks STACK Pointer Register. But, It does have STACK. Then, in my opinion, a program will still be able to call subroutines but, will be unable to return back from the subroutines....
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3answers
90 views

How can any non-primitive-recursive function like the Ackermann function be implemented on hardware?

If for-loops and function calls both boil down to jump instructions when implemented on a real machine, then how is "The Ackermann function isn't implementable with for-loops" a meaningful phrase?
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L1 Cache Missing Timing Attack

I'm trying to understand Section 3: L1 Cache Missing in the paper Cache Missing for Fun and Profit. I'm stuck on trying to figure out how the covert channel is ...
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3k views

How does the computer know whether an address contains an instruction to be executed, or data to be used in an instruction?

The question is already stated in the title.
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53 views

Doubts on Virtually Indexed,Physically tagged Cache

I tried referring a few material (videos on youtube and this link as well), but I still couldn't wrap my head around the concept. My (brief) understanding of the Virtually addressed, Physically ...
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1answer
1k views

Least Significant Bit (LSB) vs Little Endian - Are they equivalent in anyway!

For a multiple choice question: What do we call the LSB? (i)Little Endian (ii)Upper bit (iii)Big Endian (iv)Lower Bit I feel ideally none of them is a true correct choice, but my best bet was (...
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56 views

Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa [closed]

Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa in floating point notation or otherwise. We actually have to prove this is not possible. But why can't we if we have infinite ...
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1answer
543 views

Why does arithmetic left shift of negative number leads to positive number?

According to this Wikipedia article, when arithmetic left shift operation is applied to a signed number, the number is multiplied by 2. But there are certain situations where a negative number becomes ...
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1answer
58 views

Software management of TLB misses?

I'm reading an OS textbook and it was talking about TLB misses being handled by software. I'm very new to all this by the way. So there's a context switch to some kernel procedure. But surely in this ...
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135 views

Cache mapping calculation

A cache has following specifications: Block size = 16 Bytes Set size = 2 way set associative Number of sets = 128 Physical address = 23 bits, byte addressable My Questions are: 1) How many blocks ...
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1answer
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Can a CPU be replaced without interrupting the processes running on it?

When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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678 views

Does the Hack computer from “The Elements of Computing Systems” use Von Neumann architecture?

I'm reading "The Elements of Computing Systems" (subtitled "Building a Modern Computer from First Principles - Nand to Tetris Companion) by Noam Nisan and Shimon Schocken. Chapter 4 is about machine ...
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Regarding Amdahl's balanced system law

One of the paper titled "Rules of Thumb in Data Engineering" (Jim Gray et. el.) mentions some calculations based on Amdahl's balanced system law. Link to paper: https://www.microsoft.com/en-us/...
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Why is there no extensive Standards Body overseeing ISAs, Bitcodes, Code Representation, etc… as there is in the case of Unicode

There exist a vast array of prominent bitcode formats, each suited for their specific task: LLVM IR: This format is build around a XML like binary streams model, designed to be used as a common ...
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1answer
356 views

Create NOT gate from other gates

If we are given only one NOT gate and any number of OR and AND gates, then, can we simulate more NOT gates?
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912 views

Does RAM take the copy of the program or does it load programs from the hard disk?

I guess it copies, since it is a temporary memory, it will erase if power is not supplied, so, that will lead to data loss right, but still, I need clarification.
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Which memory holds the copy of the program that is to be executed?

I don't know whether it is RAM or cache; I can say that isn't the registers since their memory capacity is very small.
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1answer
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Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?

I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
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1answer
52 views

Slowdown when accessing data at page boundaries?

Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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2answers
331 views

How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
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2answers
2k views

Confusion in speed up calculation for pipeline architecture

This is an online question I am trying to solve. You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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1answer
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If the Intel Pentium processors, was not made compatible to programs written for its predecessor, it could have been designed to be a faster processor

I find this question while solving some government job question bank. If someone could provide the answer along with a little explanation it would be very helpful. Ques:- If the Intel Pentium ...
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3answers
1k views

How is an Assembly Language Processed by a CPU's Circuitry?

I'd like to have a bit more understanding of how, on a circuitry/hardware level, an assembler program works. I think I have a very broad-brush understanding of how a CPU would process machine code on ...
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1answer
499 views

Compute cache miss rate for the given code

Problem Description: We consider a 128-byte data cache that is 2-way associative ($E=2$) and can hold 4 doubles in every cache line. A double is assumed to require 8 bytes. For the below code we ...
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85 views

Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
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Problem regarding caching. Block offset, Set index and Tag

I am currently reviewing for my exam in computer architecture. I've run into a question in the old exam sets that I can't really figure out. The question is regarding caches, more specifically block ...
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1answer
45 views

Doubt on Floating Point Representation [closed]

$1-2^{-23}$ and $2-2^{-22}$ both represents floating point representation or normalised representation.But are those two represent same value or both have different value? Is floating point ...
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48 views

How to determine index being access in memory

Having 4GB byte addressable main memory in 32-bit system divided into block of size 1024 bytes. If processor wants to access a memory location 0xFC347004. Corresponding block is found in cache. ...
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2answers
109 views

In what sense are dataflow architectures non-deterministic?

The Wikipedia article mentions non-determinism in the context of dataflow architectures. Arthur Veen's paper mentions non-determinism when it elaborates on MERGE nodes as conditional constructs. Are ...
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Case where anti-dependency doesn't need pipeline stalling

While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling. But i couldnt find at example for ...
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What is tag-only forced cache inclusion called?

Is there a commonly accepted term for caches that are guaranteed inclusive with respect to tags but not data? Inclusion can be helpful to simplify cache coherence, for which use only tags need to be ...
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1answer
199 views

What uses have been proposed for overlaid skewed associativity?

In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
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What is this weird gate?

This came from a picture of something that I'm supposed to make, and I can't find it in the program I'm supposed to use (LogicWorks). It looks like it 'not's only one of its inputs, but that doesn't ...
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1answer
117 views

Problem Set Solutions/Interrupts & Exceptions/Problem 1

Using Tomasulo’s algorithm, for each instruction in the listed sequence determine when (in which cycle, counting from the start) it issues, begins execution, and writes its result to the CDB. Assume ...
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What architectural features will allow this microprocessor to access a separate “I/O space”?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition): Consider a hypothetical microprocessor generating a 16-bit address (e.g., ...

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