Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How was counted one second in computers

I would like to know how was counted 1 second in computers. I mean how machine can understand period of 1 second. Who and when resolved this problem, and more important how ?
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Find TAG Direct-mapped cache

Consider a memory hierarchy with 16GB RAM and 8KB direct-mapped cache addressed to bytes and 8-byte blocks. How many bits will be used for the TAG field? I'm not sure of my sequence: ...
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How would I go about calculating the index field / tag field?

For index field I got '9' because 2^(9) = 512 words. But I'm stuck on what the formula for calculating the tag field is... any ideas? Given a cache that holds 512 words and block size of one word. ...
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How to Calculate Clock Rate for Processor?

Please can anyone help me to solve the following question, I have no idea to solve that 👀.
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How do I solve the part (a), of the following question?

The problem I'm facing is how do I know whether the mapping is "1-way set associative", "2-way set associative", "4- way set associative", etc. Please help!
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How many RAM chips of size 256k x 1 bit are required to build 1M Byte memory

$$1MBytes =1024*1024*8$$ $$256k*1bit=256*1024$$ $$1MBytes = \frac{1024*1024*8}{256*1024}=32$$ Now my question is that for converting 1MByte to bit level we need 1024*1024*8 but 256K is not converted ...
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Code size of Instruction set Architecture

For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses ...
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true dependence Question

Let's Have i1. lw $s2,0($s1) i2. lw $s1,40($s6) i3. sub $s6,$s1,$s2 i4. add $s6,$s2,$s2 i5. or $s3,$s6,$zero i6. sw $s6,50($s1) what is the true dependence ...
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How to solve this problem of architecture and scalability?

I know this question may seem weird, mainly, why the context (OS, kind of system, etc) isn't explicit. I am studying for an exam, and, according to the studies guide, one of the questions types can be:...
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Cache (TLB) - fully associative cache

I have an exercise and I don't understand the solution. ...
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Associativity Question , Computer organization

an access sequence of cache block address of length N and contaons n unique addresses. The no. of unique block address between 2 consecutive accesses to the same block address is bound above by k. ...
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347 views

Assembly decision loops

An high level language such as C has many statements for decision and loops while an assembly such the MIPS' one has few. With slt, ...
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computer organization : finding control word length

A microprogram control unit is required to generate a total of 35 control signals. Assume that during any microinstruction, at most 2 control signals are active. The minimum number of bits required in ...
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2's complement addition with ZF/Carry/Overflow

Consider addition of two numbers when CPU uses $2's$ complement form: $$ 1\ 1\ 0\ 0\ 0\ 0\ 1\ 1\\0\ 1\ 0\ 0\ 1\ 1\ 0\ 0\\-------\\0\ 0\ 0\ 0\ 1\ 1\ 1\ 1\\------- $$ $$Carry\ = 1,\ Overflow = 0, \ ...
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953 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
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2answers
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What's the difference between Memory Byte (Mb) and Mega Byte (mb) [closed]

I am currently running my head around to understand if i am actually getting it correct or not? A memory chip with 1 byte cell size has 12 address lines. How many data lines does the chip have? What ...
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Is the front-side bus multiplier the same as how many transfers it does per second?

What I am doing: I've been reading there about front-side busses (FSB) and their cycles per second (MHz) vs. bandwidth (Millions of Transactions per second or MT/s). What I've understood: FSB's MHz ...
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How to find the definition of Computer Architecture terms in Compter Science? [closed]

To find the meaning of computer architecture terms in Computer Science do I need to use a Computer Science book? Do I need to find the computer architecture terms in a Computer Science Dictionary or ...
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2-core 2.6GHz vs 4-core 1.3GHz [closed]

If a process could run as much cores as available, which CPU is faster, a 2-core 2.6GHz CPU or a 4-core 1.3GHz CPU?
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How do I find the size of Tag and line in bits?

In direct memory management, CPU references address of 15-bits. Main memory size is 512 * 8 and cache memory size is 128 * 8. What is the size of Tag and line in bits? Block size=8=2^3 I have found ...
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What determines a hit or a miss for direct mapped cache?

I've been stuck on this for a while now, I've tried reading the related topics on cs.stackexchange as well as the textbook and youtube videos. Suppose we have a 8KB direct-mapped data cache with 64-...
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Calculate the number of instructions replaced ? [closed]

I was studying a cs book for computer architecture(computer organization and design) and I found this exercise: ...
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How do i find bits in virtual and physical address?

The question is: ...
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Approximate percentage of the memory's total operating time for refreshes while refreshing DRAM

A DRAM that must be given a refresh cycle 64 times per ms.Each refresh requires 150ns,a memory cycle requires 250 ns. What is the approximate percentage of the memory's total operating time must be ...
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Find number of platters of a given disk

I am kinda blocked trying to figure out the answer to this question. Mind helping? A manufacture wishes to design a hard disk with a capacity of 60 GB or more (using the standard definition of 1GB = ...
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How would I answer this? I recently started doing computer studies at school

is this format okay? this is my first time using stackexchange.
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How does “main memory consisting of 1Gbytes”, and “32 bit memory addresses” mentioned in the question below, relate to each other?

A computer system uses 32-bit memory addresses and it has a main memory consisting of 1Gbytes. It has a 4K-byte cache organized in the block-set-associative manner, with 4 blocks per set and 64 bytes ...
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207 views

If direct mapping scheme was used instead what will be the size of the tag field?

A computer has a 32K main memory and a 4K fully associative cache memory. The block size is 8 words. The access time for main memory is 10 times that of main memory. a. What is the size of tag field ...
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1answer
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removing write protection [closed]

I tried to format my 32 GB SanDisk pendrive. But it showed me that " the disk is write protected" . I tried using CMD but it failed. I can't format it even using safe mode. Please help me to recover ...
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3answers
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Computer Architecture, specifically Amdahl's Law

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. The question I ...
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D - Latch or D Flip Flop?

I have a diagram (http://imgur.com/cET8Q14) where it is either a D Latch or D Flip Flop. I am trying to figure out which one it is and why. If it is a D Flip Flip, I also need to know which input is ...
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281 views

Counting the number of instructions in an instruction set

An imaginary processor has the following hardware specification: 8bit data bus 12bit address bus 32 × 8bit general purpose registers e.g. S0 – ...
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How many bits does a data bus need to have? [closed]

Using the following context as an example for the calculations: Data bus connecting the processor to a memory 32 bits, considering a memory with capacity of 16kB. How many bits does a data bus ...
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How is a human brain the same as a computer? [closed]

Which functions performed by the brain equal which parts/functions of a computer? For example, human memories are like data saved to a hard drive?
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How does this instruction format limit the number of memory addresses? [closed]

I have come across a question like this. And I don't have any idea how to solve this. Suppose a machine with instruction format of the form opcode A,B,R where <...
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Calculate the storage capacity of this disk in GB [closed]

A disk pack has 12 platters ( plates) having 2048 tracks on every surface. It can store 1024 bytes per sector ( assume each track has 512 sectors). Calculate the storage capacity of this disk in GB.
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what does one million word represent in the question below?

An Associated cache and one million word main memory are divided into 256 word blocks. How many blocks are there?
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Architecture, microarchitecture and ISA in microprocessor [duplicate]

What is Architecture, microarchitecture and ISA in processor. How do they relate to each other and what is the difference between them. Elucidate their differences with examples so that it is ...
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design 10-4 compressor using 7-3 compressor and delay analyse

I need a design for 10-4 compressor (adder) using 7-3 and analyse gate and block delay. Is any reference or solution to this?
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Functions of CPU

What part of the CPU communicates with all the other parts of the processor and makes the processor faster by containing frequently used data or instructions?

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