Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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How are interrupts discovered?

In the textbook I'm reading, it states that If the interrupt is of a lower/equal priority to the current process then the current process continues If it is of a higher priority the CPU ...
Tobi's user avatar
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Could computer architecture be reworked to support switching from binary to ternary, for example?

I was investigating why computers use binary instead of ternary and, from what I understand, found it's for precision. We want to avoid getting the wrong answer when computing math, and if we were to ...
Reason's user avatar
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What exactly (and precisely) is "offset"?

Just like my previous question concerning 'hash'; what exactly is an (or the) "offset?" Is it a value or data type? Or is it an address location? I have heard it used in different contexts within the ...
Basil Ajith's user avatar
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Is there any development in continuous-value computers?

Is there anything that hints at the possibility of a (modern) continuous-value computer, since modern computers are based on discrete arithmetic? I guess the old analog computers were of this ...
mavavilj's user avatar
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What is this trapezoid-shaped logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode, which corresponds to the ADD instruction. I recognize 011, ...
committedandroider's user avatar
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How, in hardware, MIPS can access a word in the middle of an address

This is am example of a RAM address in the MIPS architecture (32 bits) I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words in ...
Revering Sumoda's user avatar
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Flowcharts vs DFA resp FSM equivalency

First I apologize if I confused therms DFA and FSM, to me it seems that is the same thing. The question is simple: Are the flowcharts (sequence, branching and jumping) equivalent to DFA resp. FSM? I ...
Wakan Tanka's user avatar
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Why do we not use continuous real quantities to represent continuous numbers

I've just been doing some pondering, and given the fact that computers already operate on fundamentally continuous physical quantities, and then we have to use transistors to turn those real ...
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Can a CPU be replaced without interrupting the processes running on it?

When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?

I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
JustAnotherUser's user avatar
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When to free physical registers

When we do register renaming to avoid WAR and WAW hazards while executing instructions, how can we know that there is no need for a physical register anymore and we can put it back in the free list?
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Why is superscalar processor SISD?

From Wiki - Superscalar processor: (Line 1): superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a ...
Kindred's user avatar
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Does Assembly Language depend on an Assembler or the family of processor?

From what I understand, the x86 family of processors understands the same instruction set and x86-32, x86-16 machine code can be executed by an x-86-64 processor because of backwards compatibility. ...
Parker Queen's user avatar
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CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
Rajat's user avatar
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Why do I get really different results with my benchmarking code I made?

I'm doing research work for my last year in high school. My work is about processors and for the experimental part i've coded an app that can mesure how many Floating Point Operation can a processor ...
NaW's user avatar
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What is random logic? Why is it needed?

I read now several articles about RISC and CISC architecture. Most are rather exuberant enumerating all the differences between these architecture, but not necessarily why things are the way they are. ...
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Combine the following IP Addresses into a single block

I was asked to combine the ip addresses into a single block: 16.27.24.0/26, 16.27.24.64/26, 16.27.24.128/25 I managed to convert the given ip addresses into binary: 00010000.00011011.00011000....
Some Guy's user avatar
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Why a separate ALU is needed, since any integer can be represented as floating point numbers?

Most of the operations in computers are using floating-point arithmetic, and why a Floating Point Unit alone is not sufficient? Can we do away with ALU? Is FP operations are resource-intensive alone ...
VEERARAGHAVAN JAGANNATHAN's user avatar
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How does the CPU know to get data from or send data to a peripheral device?

We were talking today, in Intro to Programming, about machine language. I know it's a bunch of 0's and 1's. Let's say I compile the following C++ program on an x86 machine: ...
moonman239's user avatar
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How to calculate the size of a page in a two level paging CPU?

I am having difficulties with understanding the concept of paging. As a result I've got no idea how I can solve the following exercise - I'm lacking one more equation to solve it. I've read a lot ...
Mateusz Piotrowski's user avatar
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Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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Using Amdahl's law how do you determine execution time after an improvement?

Speeding up a new floating-point unit by 2 slows down data cache accesses by a factor of 2/3 (or a 1.5 slowdown for data caches). If old FP unit took 20% of program's execution time and data cache ...
user1068636's user avatar
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Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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How does a GPU get data from a CPU?

From what I’ve read, the CPU has to send the data to the GPU before the GPU can do anything with it. But, if that’s the case, won’t any time saved using the GPU be negated by the time taken to ...
user11937382's user avatar
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Is PREFETCH an asynchronous operation?

I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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What is the difference between a microoperation, microinstruction and control word?

I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
mahesh Rao's user avatar
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
Connor Claypool's user avatar
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What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
user366312's user avatar
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How are CPU architecture and word size related?

I did lot of research on internet but couldn't get my answer. I want to know what is the difference between the word size and CPU architecture? For eg.- I read that CPU of 32-bit architecture can ...
Vinay Prakash's user avatar
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How would one use "BUT" logic in a ternary logic computer in a practical way?

Using three valued logic one can define a multitude of ternary operations. When dealing with 5:3:1[1] operations, its very easy to see how ...
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CPU cache - retrieving data from memory

Regarding CPU cache, if the CPU does not find the data it needs in the cache, I understand it then looks for it in the main memory (RAM). (Let's assume we have only one level of cache in order to keep ...
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Meaning of Steve Wozniak's epiphany on register addition/subtraction in 1975?

I just finished reading Walter Isaacson's Innovators and on page 350 there is a quote from Steve Wozniak recalling things he learned from the March 1975 Homebrew Computer Club meeting: A person at ...
ashtree's user avatar
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What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
gvgramazio's user avatar
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Origin of tFAW (Four Activation Window) in DRAM timing constraint

In DRAM timing constraints, tFAW means length of a rolling window that allows up to four row activations in same Rank. This constraint is mainly due to power budget of each rank. However, I am ...
gmagogsfm's user avatar
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Query about FP Divide latency and Initiation Interval

Latency is defined as the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval is the number of cycles ...
sai kiran grandhi's user avatar
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How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
Mirrana's user avatar
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Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
avi's user avatar
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Is there a meta-analysis of this concept anywhere?

In a textbook on systems and networks, it states "Stated broadly, a program tends to access a relatively small region of memory irrespective of its actual memory footprint in any given interval ...
Neel Sandell's user avatar
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What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
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Really confused about latency with pipelining

I finished watching a video about pipelining https://www.youtube.com/watch?v=eVRdfl4zxfI which I thought made sense. Latency is the amount of time it takes to complete each instruction. Even with ...
ahuang513's user avatar
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Do we need to check for mantissa overflow in floating point multiplication?

We do check for the mantisas overflow in floating point addition e.g. If we are adding $8.02 \times 10^3 + 9.01 \times 10^3 =17.03 \times 10^3$ i.e we get an overflow, so we shift the number right ...
Team B.I's user avatar
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How likely is it that a computer miscalculates 1+1? [closed]

Of course, normally a fully-functional computer will calculate 1+1=2. However, the physics governing the behavior of a chip is quantum mechanical. So in principle there is a certain probability that ...
Ethunxxx's user avatar
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How is parallel tag checking achieved in associative Mapping?

I originally posted this question on stack overflow and then realised it was better suited to computer science . In the book on computer organization and architecture by William stallings , in the ...
nino's user avatar
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Secondary Storage in Von Neumann Achitecture

For an assignment, I need to draw a diagram of Von Neumann architecture, and explain each part of it. All the diagrams and explanations I've seen have a distinct "Memory" block that holds both the ...
Carcigenicate's user avatar
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What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
committedandroider's user avatar
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What counts as a pipeline?

From Tanenbaum's Structured Computer Organization: Figure 2-4(a) illustrates a pipeline with five units, also called stages. If one pipeline is good, then surely two pipelines are better. ...
Tim's user avatar
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How does the Program Counter work?

I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction. But now my question is, how do you ...
Joey's user avatar
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Karnaugh map with don't care: increasing the number of groups instead of simplifying

AB 00 01 11 10 00 | x | 1 | 0 | 1 | CD 01 | 0 | 1 | x | 0 | 11 | 1 | x | x | 0 | 10 | x | 0 | 0 | x | The answer to the ...
imhobo's user avatar
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How do you go about designing a vector processor architecture for the sum of matrix products?

The following equation is a matrix expression where $B_i$ and $C_i^T$ are $n\times n$ matrices and k is a positive integer: $$P = \sum_{i=1}^k B_i C_i^T $$ So $P = B_1 C_1^T + B_2 C_2^T + \cdots +...
user1068636's user avatar
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Could I simulate the implementation of memory components

I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu. In the paper ...
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