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Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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1answer
4k views

Using Amdahl's law how do you determine execution time after an improvement?

Speeding up a new floating-point unit by 2 slows down data cache accesses by a factor of 2/3 (or a 1.5 slowdown for data caches). If old FP unit took 20% of program's execution time and data cache ...
3
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1answer
67 views

Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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1answer
231 views

How does a GPU get data from a CPU?

From what I’ve read, the CPU has to send the data to the GPU before the GPU can do anything with it. But, if that’s the case, won’t any time saved using the GPU be negated by the time taken to ...
3
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1answer
51 views

Is PREFETCH an asynchronous operation?

I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
3
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1answer
2k views

What is the difference between a microoperation, microinstruction and control word?

I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
3
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1answer
87 views

Can a CPU be replaced without interrupting the processes running on it?

When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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2answers
1k views

Does Assembly Language depend on an Assembler or the family of processor?

From what I understand, the x86 family of processors understands the same instruction set and x86-32, x86-16 machine code can be executed by an x-86-64 processor because of backwards compatibility. ...
3
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1answer
218 views

How would one use “BUT” logic in a ternary logic computer in a practical way?

Using three valued logic one can define a multitude of ternary operations. When dealing with 5:3:1[1] operations, its very easy to see how ...
3
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1answer
753 views

CPU cache - retrieving data from memory

Regarding CPU cache, if the CPU does not find the data it needs in the cache, I understand it then looks for it in the main memory (RAM). (Let's assume we have only one level of cache in order to keep ...
3
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1answer
102 views

Meaning of Steve Wozniak's epiphany on register addition/subtraction in 1975?

I just finished reading Walter Isaacson's Innovators and on page 350 there is a quote from Steve Wozniak recalling things he learned from the March 1975 Homebrew Computer Club meeting: A person at ...
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1answer
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Query about FP Divide latency and Initiation Interval

Latency is defined as the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval is the number of cycles ...
3
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1answer
6k views

How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
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2answers
3k views

Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
3
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1answer
56 views

What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
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2answers
134 views

How likely is it that a computer miscalculates 1+1? [closed]

Of course, normally a fully-functional computer will calculate 1+1=2. However, the physics governing the behavior of a chip is quantum mechanical. So in principle there is a certain probability that ...
3
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1answer
861 views

Secondary Storage in Von Neumann Achitecture

For an assignment, I need to draw a diagram of Von Neumann architecture, and explain each part of it. All the diagrams and explanations I've seen have a distinct "Memory" block that holds both the ...
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1answer
1k views

What counts as a pipeline?

From Tanenbaum's Structured Computer Organization: Figure 2-4(a) illustrates a pipeline with five units, also called stages. If one pipeline is good, then surely two pipelines are better. ...
3
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1answer
810 views

Karnaugh map with don't care: increasing the number of groups instead of simplifying

AB 00 01 11 10 00 | x | 1 | 0 | 1 | CD 01 | 0 | 1 | x | 0 | 11 | 1 | x | x | 0 | 10 | x | 0 | 0 | x | The answer to the ...
3
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1answer
196 views

How do you go about designing a vector processor architecture for the sum of matrix products?

The following equation is a matrix expression where $B_i$ and $C_i^T$ are $n\times n$ matrices and k is a positive integer: $$P = \sum_{i=1}^k B_i C_i^T $$ So $P = B_1 C_1^T + B_2 C_2^T + \cdots +...
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1answer
150 views

Could I simulate the implementation of memory components

I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu. In the paper ...
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0answers
222 views

Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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0answers
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Recommendation book to learn how computers work at a transistor level [closed]

I would like to know your book recommendations / popular books to learn how computers perform operations, store memory, process your mouse input to open a program for example (maybe not that ...
3
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1answer
268 views

L1 and L2 cache

I cannot find a to-the-point reference for my question. Am I correct in assuming that if you have an L1 and an L2 cache, typically the L2 cache linesize is larger? For the following, let's assume a ...
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4answers
212 views

How are alphabetic characters programmed into a computer?

I'm no cs student, I'm a programmer. I have a couple of questions and a few assumptions that I will make here (correct me if I'm wrong please). From my understanding is that all the sequences of 1 ...
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2answers
9k views

How is data written to RAM

From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor. When I create data (...
2
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2answers
19k views

Differences between SISD, SIMD and MIMD architecture (Flynn classification)

I have a problem with classifying certain CPUs to the proper classes of Flynn's Taxonomy. 1. Zilog Z80 According to this article on Sega Retro, Z80 has limited abilities to be classified as SIMD: ...
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3answers
551 views

Is a supercomputer more powerful than the total of all the world's computers in 2004?

The supercomputer I am researching has 2.2 petaflops and boasts total memory of 1000 terabytes and disk space of 23.5 petabytes. Is this more computing power than the total of the entire worlds ...
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2answers
5k views

Where is Program Counter (PC) stored?

Where is program counter stored? CPU caches? Also how big are these counters? What happens if that memory has been filled up? I know that it's a value that stores the next instruction for the CPU ...
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2answers
398 views

Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

Does having one larger L1 cache instead of L1 and L2 cache makes computation faster? Also will this make the CPU more expensive to make?
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3answers
171 views

What do CPUs do when a program aborts with an error?

If a very severe interrupt occurs, say a divide by zero, this will quit the program. How is this done, is there a special instruction in the processor or is it a software routine? And after quitting ...
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2answers
4k views

Does the BIOS run on the CPU? [closed]

I was just thinking about this: Does the BIOS execute on the CPU? If so, how does it handle multiple CPU architectures/instruction sets? If not, what does it execute on?
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2answers
523 views

Why does x86 has explicit register definitions, and RISC's doesn't?

For example, on x86, we have a set of general registers, each named to the function it carries out. We have an Accumulator, which is a storage for a results of different fixed point operations, we ...
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5answers
22k views

How to determine the maximum RAM capacity for an operating system?

I was curious to know what limits the max RAM capacity for an OS while reading about microprocessors being 32-bit and 64-bit. I know that limit for 32-bit OS is 4GB and for 64-bit OS is 16 Exabytes, ...
2
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2answers
881 views

How do processors fetch instructions that are longer than the word length? [closed]

From what I have read, instructions under x86 can be as long as 15 bytes. Since x86 is a 32-bit architecture (64-bit for x86-64 obviously) how does it handle these long instructions? How are they ...
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3answers
7k views

What are the disadvantages of having many registers?

IA-64 is an architecture that has 128 general purpose registers, are there any disadvantages (beside being more expensive and larger instruction size) to having many registers?
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2answers
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use of unconditional transfer of control instruction

I did not understand why unconditional transfer of control instruction is used in cpu.So if we already know we have to jump to an instruction and skip some instruction irrespective of any condition ...
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3answers
3k views

Why do we still use a Von Neumann Architecture in modern computers?

The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons. To this day the Von Neumann ...
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2answers
687 views

Can a processor without stack pointer registers, have a subroutine calls and interrupts?

Suppose a processor does not have any stack pointer registers, which of the following statements is true? It cannot have subroutine call instruction It cannot have nested subroutines call ...
2
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1answer
939 views

Where are 'Base & Bounds' registers located?

I read about virtual memory from L08/CS152 of U.C Berkeley and used to deep dive into the details of VM hardware implementation, yet didn't find any document or figure on the course specifying where ...
2
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1answer
200 views

Is every CPU instruction ultimately read and write?

Is every instruction ultimately all read or write instructions? So, how I imagine this is that every place where something can be stored can be either in a read or write state, including the CPU ...
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2answers
2k views

how can a program be OS-dependent?

I know the fact that you cannot run the same machine code on two different machines, so the software must be machine dependent (i.e Arm program cannot run on either powerpc or x86). but in reality ...
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1answer
3k views

Relationship between RAM size and 32-bit vs 64-bit word size

I know that x86 supports only 4GB of RAM, and that switching to x64 greatly increases the size of RAM you can use, but I don't understand why. Why is the maximum supported ram size related to whether ...
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1answer
4k views

Advantages and disadvantages of microcoded vs hardcoded architectures [closed]

Preamble I can't understand what are the advantages and disadvantages of microcoded processor architecture and hardcoded one. Basically what I understood is that a microcode architecture divides an ...
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6answers
777 views

Representation of unsigned integer on a little endian, big endian computer

This is a GATE 2021 exam question. If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices ...
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3answers
143 views

Do the newest computers still have ROM?

Now that many computers use UEFI instead of BIOS to boot the computer, and UEFI instructions are usually stored in a hidden hard disk partition, does this mean the newest computers do not need to have ...
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2answers
100 views

How is CPU different from GPU?

A central processing unit offers to handle various operations like calculating, watching movies, making presentation etc. While a graphics processing unit is majorly used for the purpose of video ...
2
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1answer
339 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
2
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1answer
209 views

Universal memcomputing machines (UMM)

This paper on memcomputing seems like a really big deal, but it doesn't seem to be particularly popular. They prove that their UMM can solve NP problems in P, although they don't claim P = NP. In ...
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1answer
2k views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?

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