Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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What is the avantage of having memory mapped I/O?

I can't make out what is the avantage of it comparing with the port designed I/O Is it faster? Is it more reliable? Is it cheaper?
veronika's user avatar
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What is happening during "table walk"?

I am trying to understand what is a table walk. I have found when it occurs - whenever there is a TLB miss. If no descriptor is found – TLB miss occurs and further behavior depends on the ...
roffensive's user avatar
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How are CPU architecture and word size related?

I did lot of research on internet but couldn't get my answer. I want to know what is the difference between the word size and CPU architecture? For eg.- I read that CPU of 32-bit architecture can ...
Vinay Prakash's user avatar
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Difficulty understanding the faster multiplication hardware

This is a picture of faster multiplication hardware taken from Computer Organization and Design (5th Edition). I'm having some difficulty understanding it. I was trying to simulate this for a test ...
Robur_131's user avatar
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Registers of Control Unit and Arithmetic Logic Unit

For an Instruction fetch cycle we have the flowing registers in a CPU. Memory Address Register (MAR) Memory Buffer Register (MBR) Program Counter (PC) Instruction Register (IR): Accumulator Register: ...
Alex's user avatar
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How are conditionals implemented at hardware level?

Can anyone explain how are conditionals implemented in the CPU? Is special circuitry used?
Vignesh's user avatar
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How are interrupts discovered?

In the textbook I'm reading, it states that If the interrupt is of a lower/equal priority to the current process then the current process continues If it is of a higher priority the CPU ...
Tobi's user avatar
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Could computer architecture be reworked to support switching from binary to ternary, for example?

I was investigating why computers use binary instead of ternary and, from what I understand, found it's for precision. We want to avoid getting the wrong answer when computing math, and if we were to ...
Reason's user avatar
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An imperative program is analogous to how a Turing machine works?

Since Turing machines has great influence on typical hardware architecture (Von Neumann) and both uses concept of state, is correct to say that an imperative program is analogous to how a Turing ...
Alexandre Demelas's user avatar
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What exactly (and precisely) is "offset"?

Just like my previous question concerning 'hash'; what exactly is an (or the) "offset?" Is it a value or data type? Or is it an address location? I have heard it used in different contexts within the ...
Basil Ajith's user avatar
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Is there any development in continuous-value computers?

Is there anything that hints at the possibility of a (modern) continuous-value computer, since modern computers are based on discrete arithmetic? I guess the old analog computers were of this ...
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What is this trapezoid-shaped logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode, which corresponds to the ADD instruction. I recognize 011, ...
committedandroider's user avatar
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How, in hardware, MIPS can access a word in the middle of an address

This is am example of a RAM address in the MIPS architecture (32 bits) I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words in ...
Revering Sumoda's user avatar
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Flowcharts vs DFA resp FSM equivalency

First I apologize if I confused therms DFA and FSM, to me it seems that is the same thing. The question is simple: Are the flowcharts (sequence, branching and jumping) equivalent to DFA resp. FSM? I ...
Wakan Tanka's user avatar
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How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?

In my OS course, the instructor mentioned the following: In UNIX if a parent process creates a new child ("fork") then the child is an exact duplicate of the parent. This means its memory ...
Mohammed Arshaan's user avatar
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Why do we not use continuous real quantities to represent continuous numbers

I've just been doing some pondering, and given the fact that computers already operate on fundamentally continuous physical quantities, and then we have to use transistors to turn those real ...
LSR's user avatar
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Can a CPU be replaced without interrupting the processes running on it?

When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?

I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
JustAnotherUser's user avatar
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Why is superscalar processor SISD?

From Wiki - Superscalar processor: (Line 1): superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a ...
Kindred's user avatar
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Does Assembly Language depend on an Assembler or the family of processor?

From what I understand, the x86 family of processors understands the same instruction set and x86-32, x86-16 machine code can be executed by an x-86-64 processor because of backwards compatibility. ...
Parker Queen's user avatar
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CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
Rajat's user avatar
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Why do I get really different results with my benchmarking code I made?

I'm doing research work for my last year in high school. My work is about processors and for the experimental part i've coded an app that can mesure how many Floating Point Operation can a processor ...
NaW's user avatar
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What is random logic? Why is it needed?

I read now several articles about RISC and CISC architecture. Most are rather exuberant enumerating all the differences between these architecture, but not necessarily why things are the way they are. ...
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Combine the following IP Addresses into a single block

I was asked to combine the ip addresses into a single block: 16.27.24.0/26, 16.27.24.64/26, 16.27.24.128/25 I managed to convert the given ip addresses into binary: 00010000.00011011.00011000....
Some Guy's user avatar
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Why a separate ALU is needed, since any integer can be represented as floating point numbers?

Most of the operations in computers are using floating-point arithmetic, and why a Floating Point Unit alone is not sufficient? Can we do away with ALU? Is FP operations are resource-intensive alone ...
VEERARAGHAVAN JAGANNATHAN's user avatar
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How does the CPU know to get data from or send data to a peripheral device?

We were talking today, in Intro to Programming, about machine language. I know it's a bunch of 0's and 1's. Let's say I compile the following C++ program on an x86 machine: ...
moonman239's user avatar
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How to calculate the size of a page in a two level paging CPU?

I am having difficulties with understanding the concept of paging. As a result I've got no idea how I can solve the following exercise - I'm lacking one more equation to solve it. I've read a lot ...
Mateusz Piotrowski's user avatar
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Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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Using Amdahl's law how do you determine execution time after an improvement?

Speeding up a new floating-point unit by 2 slows down data cache accesses by a factor of 2/3 (or a 1.5 slowdown for data caches). If old FP unit took 20% of program's execution time and data cache ...
user1068636's user avatar
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Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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Information theory of instruction set architecture design?

Information theory to a large extent deals with how to efficiently encode messages given a probability distribution over messages. Intuitively, it seems like we can think of machine instructions (or ...
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How does a GPU get data from a CPU?

From what I’ve read, the CPU has to send the data to the GPU before the GPU can do anything with it. But, if that’s the case, won’t any time saved using the GPU be negated by the time taken to ...
user11937382's user avatar
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What is the difference between a microoperation, microinstruction and control word?

I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
mahesh Rao's user avatar
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
Connor Claypool's user avatar
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What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
user366312's user avatar
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How would one use "BUT" logic in a ternary logic computer in a practical way?

Using three valued logic one can define a multitude of ternary operations. When dealing with 5:3:1[1] operations, its very easy to see how ...
Krupip's user avatar
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CPU cache - retrieving data from memory

Regarding CPU cache, if the CPU does not find the data it needs in the cache, I understand it then looks for it in the main memory (RAM). (Let's assume we have only one level of cache in order to keep ...
PhantomR's user avatar
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Meaning of Steve Wozniak's epiphany on register addition/subtraction in 1975?

I just finished reading Walter Isaacson's Innovators and on page 350 there is a quote from Steve Wozniak recalling things he learned from the March 1975 Homebrew Computer Club meeting: A person at ...
ashtree's user avatar
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What's the difference between dynamic and static pipelines?

I was trying to understand what a reservation table is in the context of pipelining, when I found this reference here, where the author mentions that there are static and dynamic pipelines. According ...
Humberto Fioravante Ferro's user avatar
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Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
Pieter Verschaffelt's user avatar
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What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
gvgramazio's user avatar
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Origin of tFAW (Four Activation Window) in DRAM timing constraint

In DRAM timing constraints, tFAW means length of a rolling window that allows up to four row activations in same Rank. This constraint is mainly due to power budget of each rank. However, I am ...
gmagogsfm's user avatar
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Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
danb's user avatar
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Query about FP Divide latency and Initiation Interval

Latency is defined as the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval is the number of cycles ...
sai kiran grandhi's user avatar
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How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
Mirrana's user avatar
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Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
avi's user avatar
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Is there a meta-analysis of this concept anywhere?

In a textbook on systems and networks, it states "Stated broadly, a program tends to access a relatively small region of memory irrespective of its actual memory footprint in any given interval ...
Neel Sandell's user avatar
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What's the average number of transistor switches needed to do an N-bit x N-bit multiply?

I want to know how switch-efficient a multiplier can be. If I need to do many $N$-bit by $N$-bit multiplies, and each bit is determined by flipping a coin, what's the average number of transistor ...
abergal's user avatar
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Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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