Questions tagged [cpu]

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What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?

I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
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CPU overused vs RAM normal usage, RAM overused vs CPU normal usage

I got asked this question in an interview, where they showed me graphs of CPU being overused and RAM being normally used, and graphs of vice versa. What deductions can we make from this, and how can ...
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What course in CS deals with the study of RAM, CPU, Storage?

I watched the Crash Course playlist of Computer Science. It was teaching about RAM, CPU, Storage etc but I felt it was way too fast and only people who have studied the course first hand understood it ...
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Building an ALU on nandgame's website

I'm working on nandgame's website found here. I'm working on the ALU and here is an image of my implementation: My Implementation: And I compared it to this website's solution: Solution However when ...
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How does the Fetch-Decode-Execute-Reset (FDER) cycle work?

How is this different to the Fetch-decode-execute (FDE) cycle? I have an understanding of the FDE cycle and how the CPU works, although I came across a FDER cycle, when reading about the CPU ...
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
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Is address bus size same as physical address size and is that the same as word size?

I am having some confusion between address bus size, physical address size and word size however (I do understand that unit of memory access is word and when word size is one byte then it's known as ...
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How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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How is CPU different from GPU?

A central processing unit offers to handle various operations like calculating, watching movies, making presentation etc. While a graphics processing unit is majorly used for the purpose of video ...
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What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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Cores, threads and sockets: what does it mean the calculation $T = tcs$ and the number on windows task manager performance?

Well, suppose then we have an CPU system such as: Thread(s) per core $\equiv t$ : 4 Core(s) per socket $\equiv c$: 4 Socket(s) $\equiv s$: 1 Then, we must to perform a simple ...
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1answer
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Is x86-64 is just an alias of EM64T?

I was reading a book which describes a historical perspective: Pentium 4E (2004, 125 M transistors). Added hyperthreading, a method to run two programs simultaneously on a single processor, as well ...
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What subfields in computer sciences may one study without learning Object Oriented Programming?

What subfields in computer sciences may one study without learning Object Oriented Programming or is there some kind of degree in Computer Science without the OOP knowledge requirement? Is there a ...
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CPU Registers and Computation

How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit? For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
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modeling DNS server CPU utilization on simulator framework

I'm creating my simulation framework, the DNS system. I have two related questions about the name server. I would like to know how much time the Authoritative Name server spends time to resolve one ...
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How are replacement policies implemented?

Suppose there is a set-associative cache using LRU or ARC replacement policy. What implements these policies? Is it a hardware module or is there a soft doing this?
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Help with performance and speed-up question related to number of cores and their areas

There is a question in my exam that said: Consider the following three processors (x, y, and z) that are all of varying areas. Assume that the single-thread performance of a core increases with the ...
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Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the architecture most likely to have?

Working through some material on CPU architecture and am unsure on the following question: Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the ...
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Are interrupts only found in BIOS?

I may be misunderstanding here-- but are interrupts only found in BIOS and not UEFI systems? More context: "Through standardized calls to the BIOS (“interrupts” in computer parlance), the operating ...
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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
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Preemptive priority scheduling problem with same priority

So if T1(priority 3, arrived first) was preempted it is put back to the runqueue. If there is already T4(priority 3, arrived fourth) inside the runqueue, which one of these two will be handled first?! ...
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Where is the register position in a CPU (real image illustration)?

I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
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How many clock cycles

Actually it differs from CPU to CPU but it is possible to choose a mainstream CPU technology used in moderate servers or home computers. How many clock cycles it takes to read a file of 50KB from ...
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Relation between size of address bus and memory size; memory Segmentation in 8086

My question is related to memory segmentation in 8086. I learnt that, 8086 has a 20 bit address bus. And so it can address 2^20 different addresses. Which means it has an memory size of 2^20, i.e, ...
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Textbook on how processors are actually structured at the circuit level

I am looking for a textbook that helps me understand how basic digital electronic units are used to build complicated integrated circuits. I have looked online for textbooks, but what I have found ...
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1answer
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When does kernel accessing virtual memory cause problems

I'm working with the CPU Pintos and have a question that is: In which situations can the kernel accessing the data in virtual memory via a pointer lead to problems? And how do you avoid them? I know ...
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How to learn how CPU works in details

I've watched multiple videos and read posts regarding modern cpus and how they work. However, those ones very rarely touch the problem on the very basic level. Like I've read about transistors and ...
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Neural branch predictors linear, classical predictors exponential, in resources?

Wikipedia states: The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource ...
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1answer
55 views

Information theory of instruction set architecture design?

Information theory to a large extent deals with how to efficiently encode messages given a probability distribution over messages. Intuitively, it seems like we can think of machine instructions (or ...
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Reactiveness, cpu and caches

I was messing around with a reactive-based frameworks and found it very expressive. Unfortunately, most of them are using techniques that are not very efficient on CPU cashing mechanism such as ...
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118 views

Advantages of Preemptive Scheduling

I'm currently studying for an exam which includes operating systems. I'm solving the exams from previous years and I'm stuck on a particular question: "One of the advantages of preemptive scheduling ...
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Direct mapped cache example

i am really confused on the topic Direct Mapped Cache i've been looking around for an example with a good explanation and it's making me more confused then ever. For example: I have 2048 byte ...
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1answer
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A microkernel fully hardcoded in hardware?

Does there exist a (micro-)kernel of an operating system that is fully implemented in hardware? That is, a kernel that is not stored in RAM, and loaded into CPU registers after an interrupt or system ...
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Deep pipeline - cpu architecture

I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance. While reading about vector instruction, I encountered the term deep ...
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How to make single cycle processor pipelined?

I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design. I suppose, that I should answer that what should be changed on ...
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1answer
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What happens with register usage in deeply nested functions calls (in theory)?

I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
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How many registers does a computer *need*?

I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
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Why no context switch is required in case of spinlock in operating systems?

I have a query regarding the fact that how Spinlocks are advantageous in terms of context switching ?
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Why does cpu benchmark increases faster than cpu frequency?

Since duration of an instruction is just the number of cpu cycles needed times the time of a cycle, which is the inverse of the frequency, I do not get why the ratio of cpu benchmark of a two ...
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What is a GPU year?

I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years". What is a GPU year? How long is that?
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Why the multiplier and quotients can not store in the ACC?

When I study the Arithmetic Unit, there is the below information: there I have some questions: Why the multiplier must store in the MQ and the product must divide ...
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
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Confusion in speed up calculation for pipeline architecture

This is an online question I am trying to solve. You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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468 views

Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
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How to calculate average waiting time for round robin cpu scheduling?

I have tried to calculate average waiting time for the below details there are two answers I'm getting using two methods I'm not understanding which one is correct? The time quantum is 2 This is the ...
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2answers
123 views

Could all CPU instructions get fundamentally faster if a better multiplication method was developed

I was reading the article Integer multiplication in time O(n log n) by David Harvey and Joris Van Der Hoeven, 2019. Could this discovery increase the throughput of future CPU's? If so could we ...
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Compiler instructions to sync core caches: are they really needed?

I have read reviews of this book, and quote the following from one of the reviews (emphasis mine): Other than straining your eyes with old-styled C++, you can read such misconceptions in the book ...
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What architectural features will allow this microprocessor to access a separate “I/O space”?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition): Consider a hypothetical microprocessor generating a 16-bit address (e.g., ...