Questions tagged [cpu]

CPU, stands for Central Processing Unit. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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Logical vs physical address program loaded into RAM, how re-mapping done?

What are common primary mechanisms to "re-map" between physical memory in RAM, and the addresses used in a program before it is loaded into RAM? In image below for example, the LOAD 12 ...
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Superscalar design on SimpleScalar simulation

I've learnt theoretically Computer Architecture at uni.However I can't wrap my head around it in practice. I am using Simple Scalar tool to simulate a benchmark program with configurable computer ...
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MIPS pipeline: MEM stage takes one cycle?

Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle: 1 cycle to read a register 4 cycles to reach to L1 cache 10 ...
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How many clock cycles are used to run my code?

Suppose that I want to know the number of the cycles of cpu clock that uses to run a specific code written with a specific programming language, like Python or others. Can I do it? I mean, do you have ...
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Which part of the CPU is responsible for executing instructions

I was reading about the machine cycle. Everything was clear until I started with the execution of instructions. I know how an ALU and a CU work. I'm also aware of the process of fetching and decoding. ...
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How does a CPU do function calls?

Besides basic instructions for a general-purpose computer (binary arithmetic, move instruction, and jump on condition), it seems you can't implement a universal turing machine (is that even the right ...
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Do modern computers prevent instructions being executed by audio? If so, how?

Most know that early phones and modems, and still, fax machines, sent information through the use of tones. This got me thinking - could audio be a viable vector for executing instructions by a bad ...
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Why we need CPU registers with pipeline?

I understand how CPUs work in general in RiscV, but things got a little complicated with pipeline and I don't get it why we need registers at all. For example, let's look at: When the ALU's input was ...
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Alu architecture of a Hack Computer

I'm currently studying the ALU architecture (of a Hack computer) and how it works. As part of my assignments, I have been asked the following question: If we want the ALU to compute the function y-1, ...
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Is it possible to build a computer whose "ALU" is a single NAND gate?

I am not asking about if it is possible to build a computer using only NAND gates, since that question has been asked infinite times. I wonder if it is possible to replace the “ALU” in the cpu of a ...
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What is related to the no of instructions a CPU can handle at one time?

Which of the below choices is related to the number of instructions a CPU can handle at one time? A) 32bit word size B) 3GHz clock speed I think should be (A). 2^32 instruction at one time?
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What are the width of data/control/address bus for a 32-bit CPU?

Are they exactly 32bits for a 32-bit CPU?
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Mathematical models of computation that capture more advanced OS and CPU design features

The universal Turing machine is the standard theoretical model of a stored-program computer. While in one sense as general as possible (Turing completeness), it doesn't explicitly contain many of the ...
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Supercomputers have millions of CPUs or cores. Is there a central chip or CPU that controls all the cores?

What device integrates and coordinates all the data from millions of CPUs/cores in a supercomputer? To call these cores CPUs (Central Processing Unit) seems wrong when they are not central at all but ...
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8085 microprocessor connection of CPU data bus with RAM data bus

What would happen if the CPU data-bus bit 2 is connected to the RAM data-bit 5 and CPU data-bus bit 5 is connected to RAM data bit 2? Assume the rest of the connections are all right – explain.
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CPU utilization estimation

In the Modern Operating System by Andrew Tanenbaum, Herbert Bos the authors provide their explanation of the concept of CPU utilization in the following way: A better model is to look at CPU usage ...
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Do number of registers and width of register have to be the same?

I am studying Computer Architecture with MIPS-32. The example system has 32 registers with each register having a width of 32 bit. If I would want 128 registers instead of 32 registers, would I have ...
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How many percentage of total transistors in a CPU are used in each component?

I'm learning the basics of computers, and now trying to get some oversight of complexity of a CPU. Is there a rough trend for how transistors are allocated in a CPU? Intel 8008 for example, has 3500 ...
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How a processor scales in terms of components

I'm still very early in understanding some computer science basics. I find it easiest to learn things when I have some oversight of what I can expect. Is there any trend to the number of logical gates ...
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Is it possible to use one of the two processors for ML acceleration?

I have two processors (two different physical processors) with base frequencies 3.2 Ghz and 4.0 Ghz. I want to ask if there exist a method which I can use to the 3.2 Ghz processor for ML acceleration ...
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How can an instruction be fetched every cycle?

From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
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What determines bus speed?

I would like to know what determines bus speed in a CPU. I know about bus width, that all makes sense, but since electrical pulses travel at light speed I don't understand why bus speed is measured ...
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Do more registers increase clock cycle time?

While reading a book on computer organization, I ran into a design principle stating that "smaller is faster", indicating that fewer registers means less clock cycle time. Could you prove ...
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Data transfer between CPU, RAM and secondary storage

Could someone explain me how the CPU address the secondary storage? If the CPU needs data that are stored on a HDD (for example), could the CPU address the HDD directly? And the data are transfered ...
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Memory Address Lines

I am reading a text book by David Tarnoff and there is something I do not understand, the section is on CPU and memory. The book states that the number of address lines going into a memory device ...
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What would happen if while making a connection between memory and CPU, the address lines get's interchanged

While making a circuit connection between Micro Processor and Memory Chips, the Address Lines A0 and A1 got interchanged. Means A0 of address bus got connected wrongly with A1 of Memory chip and A1 of ...
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About clock cycles executed

i have a pretty basic question, but for example a cpu clock at 3ghz, does that mean it can do 3 billion cycles per second, or does it every second always will make since 3 billion cycles?
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interactivity between RAM and CPU

I have a very silly question, when data is transferred from the RAM to the CPU is this data transferred "copies" of the original data stored inside the RAM?
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Why interrupts can help to increase the efficiency of a user program that contains many I/O operations?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. I get the general mechanisms of how interrupts are handled in computer systems, but the results ...
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Why do the following algorithms for Quadratic Primes perform so differently?

I'm trying to solve for https://projecteuler.net/problem=27, and I have to optimize one part of the implementation from slow() to fast(). Why do they perform so differently? I'm guessing branch ...
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What is a Trace bit?

What is a trace bit in Processor Status register, I can't find any resource that describe about how it work, for now all I could find is that it take two bits 0,1 for Trace on/Trace off mode. Can ...
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How do you "time" the measure of binary streams?

This is just something I've been wondering just out of curiosity. I apologize if this doesn't fall under the category of this forum, and if so feel free to divert me :) Whenever a computer does ...
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Running an application that needs 6 threads on dual core processor

If a dual core processor have 4 threads, then what will happen if i run an application which uses more than 4 threads? And just to make sure i'm understanding what are threads in a cpu, when an ...
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CPU scheduling Decisions

Operating System - CPU scheduling Decisions The question above talks about why CPU scheduling does not take place when ready to running. But I wonder why CPU scheduling does not take place when new ...
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how does the program change the clock speed of the processor?

bios is a program that checks all devices and starts the bootloader. but how does the CPU sync with the motherboard if the CPU clock settings are stored in the BIOS? Does the BIOS have CPU clock ...
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What would happen in this priority-based round-robin CPU scheduling algorithm case?

I've been implementing some kind of CPU Scheduling Algorithms in Python. And I am really confused with one of the cases what'd be implemented in this case. Let us assume that the time quantum is 10. ...
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How is conditional jump implemented in the CPU?

After reading the question I'm still not sure how CPU does branching. I understand that we have an instruction counter which points to the current instruction. And after performing conditional jump it ...
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Are EAX , EBX registers 64 bit in length in modern processors [closed]

The EAX, EBX and ECX registers on a cpu are they 64 bits for a 64-bit cpu ?
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Why are registers name in assembly cryptic

Why are registers named so short - EAX, EBX,...etc They could have easily made the names more descriptive rather than encrypted like that.
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Memory addressing rapidity

I've got a few questions related to the different types of memory that we can find: To my understanding, since there are registers that are close physically to the CPU, these are much faster to access,...
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Can x86 Instruction Set be changed with microcode update?

How I understand microcode translate an instruction to microinstructions. And CPU has a unit that stores all possible of microinstructions. These microinstructions can be changed, because it load ...
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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Can a single core processor be MIMD?

I was wondering for if a single core processor can be MIMD? or MISD? or SIMD? I thought MIMD's requirement is multicore, but I am not sure about this
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How do computers *really* work? (at the most basic level)

While learning about computers I will read about RAM and Storage and the CPU, and while these explain the architecture of a computer and how parts of a computer work together, I still don't understand ...
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About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor. We do assume that ...
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Metrics on which Clock Cycles Per Instruction(CPI) depends

In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this: The term clock cycles per instruction, which is ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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How the task is divided between multiple cores to perform in multiprocessing systems?

I am trying to find how single task is divided between two cores? what are the methods makes them work at the same time without interfering with each other?
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Conditional branch instruction

How is a conditional branch instruction implemented in hardware? The instruction checks the sign bit, how does it decide to load pc with the branch address or increment pc to the next sequential ...

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