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Questions tagged [cpu]

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CPU timeslicing calculation

Out of a 1000 time slices the OS itself uses 100 of these (assume that these are spread at regular intervals over each second) it can make 900 such time slices available for virtual machines each ...
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How to calculate average waiting time for round robin cpu scheduling?

I have tried to calculate average waiting time for the below details there are two answers I'm getting using two methods I'm not understanding which one is correct? The time quantum is 2 This is the ...
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Could all CPU instructions get fundamentally faster if a better multiplication method was developed

I was reading the article Integer multiplication in time O(n log n) by David Harvey and Joris Van Der Hoeven, 2019. Could this discovery increase the throughput of future CPU's? If so could we ...
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Compiler instructions to sync core caches: are they really needed?

I have read reviews of this book, and quote the following from one of the reviews (emphasis mine): Other than straining your eyes with old-styled C++, you can read such misconceptions in the book ...
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What architectural features will allow this microprocessor to access a separate “I/O space”?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition): Consider a hypothetical microprocessor generating a 16-bit address (e.g., ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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Propagation delay vs max frequency

Do you agree with the following computation - and if no, can you explain why ?, if we make the assumption the the size of a CPU chip is 1 [cm] (which I am not sure, but I guess is not much bigger?): ...
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How does the cpu know which process to wake?

In general, my understanding is: the cpu is executing a process/thread until either it is interrupted, the scheduler kicks it out, or it's waiting for something else (I/O for example), when it's put ...
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Explain in laymen terms - How do modern programs translate into machine code

I'm sure this will benefit anyone else on a computer science fundamentals back-fill journey.. I'm slowly learning Assembly and while I'm starting to understand the core of it (MOV, JUMP, etc) and can ...
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Which unit (control unite or logic unit) issue instructions of load/store?

I learned that the CPU is composed of two units and the machine’s instructions can be categorized into three groupings: (1) the data transfer group, (2) the ­arithmetic/logic group, and (3) the ...
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How are words assigned in machine language?

So, if you have an 8-bit computer and it can perform a fetch cycle, meaning it can access its memory, how do you create words the computer understands. If LDA "load the accumulator" is in the ...
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multithreading - duration of jobs

" How long will it take for 2 jobs to complete if they're running in parallel, knowing that both have a total of 20 minutes of CPU usage time and 50% IO" I calculated the CPU usage: ...
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interrupts in operating system

Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instruction ...
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ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
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1answer
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jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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Who decides that process needs cpu time or not?

I wonder how does particular process gets CPU time or resources whenever it's required to execute some instructions? When a process is in the idle state or waiting for input, it's not occupying the ...
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How Does an Operating System/BIOS Determine Physical Addresses of Devices?

So I understand that in every computer, the Operating System, the BIOS, or both will determine the physical addresses of the hardware devices and then translate that into virtual addresses. What I don'...
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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Any CPUs using value prediction, dynamic instruction reuse?

There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
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Number of memory cycles stolen for transferring one word

The storage area of a disk has the innermost diameter of 10 cm and outermost diameter of 20 cm. The maximum storage density of the disk is 1400 bits/cm. The disk rotates at a speed of 4200 RPM. The ...
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How does an accumulator with an upper and lower half work?

In the article "The IBM Magnetic Drum Calculator Type 650", originally published in Vol. 1, Issue 1 of Journal of the ACM, the article describes a computer architecture with a single accumulator ...
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Bytes addressable processor

In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
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Does each assembly language correspond to one instruction-set-architecture?

This is a quote from wikipedia: Each computer architecture has its own machine language. Computers differ in the number and type of operations they support, in the different sizes and numbers of ...
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Registers in a CPU

https://en.wikipedia.org/wiki/Processor_register So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
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Do most computational efficiency increases due to increased transistor count in the last 70 years depend on some kind of parallelism?

Modern personal computers as far as I understand have increased in power (measured informally by ability to compute “more demanding programs”) due to two “broad factors”: decreased transistor size (...
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Why are word sizes in modern CPU’s a power of 2?

Word size of most modern cpu’s is 32 or 64 bits. Both are a power of 2. This looks “intuitively reasonable”, because a bit has 2 states, but I don’t actually have a hard argument for why this is the ...
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How are CPU architecture and word size related?

I did lot of research on internet but couldn't get my answer. I want to know what is the difference between the word size and CPU architecture? For eg.- I read that CPU of 32-bit architecture can ...
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1answer
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micro programming and hard wiring

I have a question about the details of microprogramming and hard wiring in CPU architecture. in hardwiring, we write a code the compiler translates it to the ISA. then ISA is run in the hardware. in ...
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Why does the explanation of auxiliary carry flag differ from the article to article?

These two images are from Google search. AUXILIARY CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry occurred from bit 3 to bit 4 of the A Register during the ...
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Does using micro-operations require a higher clock rate than listed

Say we have a modern (Skylake, say) Intel CPU running at a fixed 5GHz clock rate. Since Intel CPUs run micro-operations internally and reaches > 1 instructions per cycle, it needs to be able to run ...
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accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
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What are data address generators?

I have come across the term Data Address Generator (DAG), which is used in Digital Signal Processors (DSPs) for memory access. What I do not understand is why can't memory be accessed directly with ...
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2answers
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Difference between delayed branches and out-of-order execution

I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
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Are multiple interrupts generated when I hold down a key on my keyboard?

When I hold down a key on my keyboard, a continuous stream of characters is generated and is displayed on the text editor, Now since pressing a key is a hardware interrupt, so does holding down a key ...
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Why does parallelising slow down this simple problem against looping through all the data?

I've been using multiprocessing and parallelisation for the first time this week on a very large data set using 32 CPUs. I decided to explore it for a smaller task just to see if I could learn ...
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Is the longest datapath really the limiting factor on clock cycle speed?

I've been watching a lecture series on computer organization and one of the lecturers statements is something along the lines of 'the clock cycle can only be as fast as the time it takes to complete ...
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What can give physical access to CPU?

If an attacker has an unlimited physical access to CPU, but does not have access to memory, including RAM, can he attack and gain access to the user's data? I heard the opinion that this is ...
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Little Man Computer Simulator Input Code

I'm just learning about the Little Man Computer CPU simulator, and am using a version online here: http://peterhigginson.co.uk/lmc/ The instruction set used by the simulator is the same as the one ...
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Valid bit incoherence between TLB and Page Table

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
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CPU scheduling Algorithm SJF VS SRTF average waiting time?

Let's say we have two CPU scheduling algorithm as SJF and SRTF and we have a arbitrary pool/set of processes with different ARRIVAL TIME and CPU BURST, then what CPU scheduling algorithm will result ...
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Compilation speed dependent on CPU?

Is the speed of compiling software very dependent on the CPU? I know this question is a bit broad, but I'm to find an answer to the case described below. If I download a software project that makes ...
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Virutalization of peripheral device

I have this question to answer: "Please shortly explain how an interface virtualizes a peripheral device to the CPU." I don't really understand what the question is asking for. I know the theory ...
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What does machine code actually look like while being run?

When machine code is actually being executed by hardware and the CPU, what does it look like? Would it look like binary, as in instructions being represented by ones and zeros, or would it be ...
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Please HELP me understand how the ISA works and how it is implemented with the microarchitecture

How is an ISA written? Is it just a bunch of binary combination encoding presets that is stored onto RAM? In other words, is it basically a “dictionary” of binary being defined as an instruction ‘word’...
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predication execution, branch prediction

Below is a paragraph from a book. In an ordinary superscalar processor, we would use branch prediction to guess which of the given instructions is to be executed, and go down that path. If the ...
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In regards to CPU instructions, why is the result of an operation stored in the source register?

Specifically when it comes to R-Type instructions, the format is operand, sR1, sR2, dR where sR1, sR2 are source registers and dR is the destination register. What I don't understand is why the ...
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A restatement of Moore's law that takes into account quantum computing

The first line of the Wikipedia article on Moore's law states that Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years As ...
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1answer
637 views

MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion

I have question about the ALUOp control signal. When doing R type instructions, 31-26th bits are all 000000. What decides the instruction is actually the func field of 5-0th bits. In that case, I ...
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How can a 16-bit or more processor store a byte in a byte-addressed memory

I am confused as to how a 16-bit (or 32, 64) processor can store multiple adjacent bytes at once without supplying multiple addresses For example say we have (16-bit processor) 0xABCD starting at ...
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How does the processing happen in a CPU when it uses Virtual Memory?

I am just trying to visualize how computers work with Virtual Memory/Address. Assume there is a program on the disk that looks like this: ...