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Questions tagged [cpu]

CPU, stands for Central Processing Unit. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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Multiplying and Dividing Binary data

So in school today we were learning about Binary shifts to the LSL#$n$ and RSL#$n$, where $n$ is an integer. I shifted a binary number to the left using the logical shift operation, hence multiplying ...
Marx Carton's user avatar
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I1 writing back to memory, while I2 currently executing on value depended on I1. How is result coherency maintained?

question regarding OOE. Imagine two instructions mov %rax, [an_address} // I1 mov [an_address] %rbx // I2 I1 makes it into the execute stage of an intel CPU. And ...
Rayyan Khan's user avatar
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Why does ISA includes instruction for logical operation?

I'm a junior student in Electronic Engineering. Recently, I learned about Gödel's incompleteness theorem. One of the concepts related to this theorem is Gödel numbering, which shows that every logical ...
MS Keane's user avatar
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RAM architecture vs. CPU architecture

I have learned that initially PCs had 8-bit memory architecture and that 1 byte (i.e. 8 bits) was the "basic" memory unit because 8 bits was exactly the memory space required to encode any ...
Jan Stuller's user avatar
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Is memory barrier NECESSARY for memory consistency?

After reading Memory Barriers: a Hardware View for Software Hackers, I came up with a point which I am not sure of its correctness, as posted in the title. I came up with this point because of ...
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Is there a delay between two commands to read data from RAM?

Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
Slaycapь's user avatar
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Byte addressing and alignment

With byte addressing, the CPU can access a single byte. But how does this access happen during alignment? As I understand it, if a CPU needs to read an unaligned byte, it reads the word starting from ...
Slaycapь's user avatar
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Are modern ram architectures (DDR4 or SDRAM) Multi-port or Dual-port?

So I recently learned about dual-port and multi-port RAM but I tried doing some research on modern RAM architectures and if they use it but I couldn't find anything on it.
Cookie Infinity's user avatar
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Why do benchmark results vary at all?

Benchmarking typically consists of getting the current CPU time, executing test code a large number of times, and then subtracting the new CPU time from the previous one. However when you benchmark ...
CPlus's user avatar
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How CPU uses wider address bus than register size?

i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). ...
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Memory addresses requested by CPU vs Memory Address Provided to DRAM

So, i just got through studying DRAM architecture. I learned that a row address, column address, bank number etc are provided to the DRAM during a read operation. Based on the address provided, 64 ...
Alice's user avatar
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Step in RISC-V program on a Pipelined Processor

I struggle to understand a step in the following solution to a RISC-V exercise. Exercise: a pipelined RISC-V processor with no data forwarding paths executes the following program. For each ...
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When a CPU copies instructions from storage into RAM how does it jump to instructions no longer in RAM?

When a CPU needs to get more instructions from storage and copies them to RAM, how does the CPU jump to previous instructions that are no longer in the RAM? Would it have to copy the old instructions ...
Thenboy's user avatar
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Cache Miss in First Private Cache but Hit in Shared LEvel 2 Cache: Does it Result in a Penalty?

In the context of Shared Memory Multiprocessor (SMP) systems with different cache levels, if a cache miss occurs in the first private cache but is followed by a hit in the second shared cache, would ...
First_1st's user avatar
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Has there been a processor architecture that included commands that move arrays of data in the memory with one opcode?

In traditional processors one move operation can at most move one word between memory locations and optionally increment or decrement the registers which point to those memory locations. In x86 ...
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Why does Elbrus use VLIW architecture?

I find the Russian Elbrus CPU fascinating. It seems that it is fairly decent at performing calculations, and security. This is likely as it is heavily specific for military and financial industries, ...
securityauditor's user avatar
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7 answers
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Mathematical benefit to use CPU/memory that increases by powers of 2 as 8-bit, 16-bit, 32-bit, 64-bit, etc?

Historically, processors often increase in bit-size by powers of 2, such as 8-bit, then 16-bit, 32-bit, 64-bit. Although this has not always been the case, it is a well known trend. One benefit is ...
BipedalJoe's user avatar
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Why aren't all smaller components of 64-bit registers accessible and readily usable?

A register in a CPU can be much more well utilized if it could be divided and its parts can be used independently. For example, if you need 8 8-bit values, you could just use a single 64-bit register, ...
user1345541's user avatar
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How to find optimum number of cpu cores for a workload

Following bar graph shows maximum percentage cpu utilization of F16sv2 (16vcpu &32GB) azure virtual machine in last 30 days. Only sometimes CPU usage goes more than 60 percentage. How to find the ...
Amal's user avatar
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What is the reason or advantage of having special purpose status flags for the result of comparisons? [duplicate]

The C semantics treat the result of a comparison or any true/false operation as just an int ...
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Roles of 80386 MMU Paging Unit and similarity with modern CPU MMU

While searching for the structure of the MMU, I found the image below (80386 Internal Architecture). I have three questions. Q1. I'd like to know the roles of 'Adder', 'Page Cache', and 'Control and ...
W298's user avatar
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How does the program counter "know" when the fetch cycle is complete?

So my understanding of updating the PC is as follows: Put memory address indicated by PC into memory address register Load the contents of the address pointed to by memory address register into ...
Robotic_Cow's user avatar
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3 answers
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Logical address vs physical address

I have been trying to understand the logical and physical address of some data/instruction the logical address is a address generated by the CPU during a execution cycle.So if I write this code ...
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Neural networks as building blocks of a computer

I think I have developed a logic circuit which by using combinational logic and flip flops learns to perform the XNOR logic between 2 bits.It is a kind of state machine. Suppose we built a computer ...
Cerise's user avatar
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Why is handling word sizes smaller than the native size of a processor sometimes slower?

For example on modern (32-64 bit CPUs), some sources say that manipulating a 32-bit or 64-bit integer will actually be faster than manipulating an 8-bit or 16-bit integer. This the reason for the <...
CPlus's user avatar
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Understanding the Relationship Between CPU Registers Amounts and Maximum RAM in 32-bit Architectures

To my knowledge, The number of CPU registers can tell us the maximum RAM we can have. I am only talking about physical memory, no virtual memory or virtualization in my question. A 32-bit CPU ...
Ahmad Addas's user avatar
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Sequence counter in a hardwired control unit

I have been studying the structure of a hardwired control unit and at 8:57 of this video we get a basic block diagram.What does the sequence counter do exactly?
Cerise's user avatar
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Can a branch be pipelined with certainty if the branch condition can be known significantly before the actual branch?

A common issue with CPU performance is that pipelining requires the knowledge of what will come next, and what comes next can only be known once a branch condition is evaluated, so that instructions ...
CPlus's user avatar
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RISC-V execution model

I'm reading a text book on CPU architecture and I have something that confuses me: The text book defines 4 different instruction execution models in CPUs, Stack (where a CPU only has a stack and is ...
anisgh's user avatar
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Why do these 8 bit registers use 16 I/O wires for input and output to the bus? Why not use 8 wires for both input and output?

I'm looking at this diagram from Ben Eater's "8 bit computer" tutorial What's the need to use separate 8 wires for only data input, and another 8 wires only for data output? Why not use only ...
Ken Kaneki's user avatar
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Logical circuit for priority resolution in interrupt controllers (with configurable priority, not fixed)

I'm interested in what the typical solution is for priority resolution in interrupt controllers. I assume a hardware logic circuit is used, and not software. For interrupt controllers with fixed ...
BipedalJoe's user avatar
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1 answer
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Are edge-triggered interrupts "hardware polled"?

Thanks in advance for assistance and patience with my hardware naivety Reading the below answer about the NMI on pin 6 for an Apple 6502, and the signal on the pin falls from high to low, how does ...
Alexander Hunter's user avatar
1 vote
1 answer
96 views

Is a CPU with a hybrid Instruction Set Architecture (ISA) possible?

Is it possible to (theoretically) develop a CPU having a hybrid ISA such that half of the cores in it use the x86 architecture and the other half uses the ARM architecture? The x86 cores would run the ...
ArijitKD's user avatar
-2 votes
2 answers
167 views

Are there any radical approaches in CPU development?

I have a desktop PC with the CPU Intel I7-12700F with 180 TDP, the CPU fan Zalman CNPS10X extreme, and Windows 11 and my problem is that The CPU cooling causes much noise when simple tasks are being ...
cpuObtainer's user avatar
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1 answer
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Can a CPU instruction be split into 2 inputs?

Let's say there was a CPU with an input bus of 4 bits and the 4 bits are the opcode then the next 4 bits are the operand. It would just be an 8-bit instruction split in two. Is this possible and how ...
Thenboy's user avatar
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2 answers
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How does a CPU jump to a instruction thats no longer in ram?

Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
Thenboy's user avatar
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I Don't Understand Nothing About Operating Systems even After reading books

I'm a programmer, let's start by that. The question may sound really broad, and in fact it is. I'll list some things that I know, and some other things I've doubts about under the form of questions. ...
gmmk's user avatar
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Dependency in pipeline

Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous ...
4DescarTes's user avatar
-2 votes
1 answer
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How a computer works?

I know that a computer can be mechanical, screws/nuts or even water/pipes. Of course, it would be slow and big, but it doesn't have to be electric, transistors, etc. How can a machine like this do all ...
user157635's user avatar
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A question about cpu utilization

Here's a question in the OS textbook about calculating the cpu utilization. I've tried to write down the (A) by myself as below. ...
samli50801's user avatar
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0 answers
67 views

Can compilers improve performance in real workloads by inserting prefetches in their output?

Prefetching is a task that the compiler feels like it should be suited for. Prefetching requires knowing in advance what data the program is about to load, and the compiler has a ton of information at ...
Narrateur du chaos's user avatar
4 votes
2 answers
1k views

How efficient is register renaming?

As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
Narrateur du chaos's user avatar
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3 answers
103 views

Is this how endianess work relative to memory?

So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things. Here is how I look at ...
Jess Chan's user avatar
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How are setup and hold and timing constraints handled when reading an address from memory?

When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, ...
BipedalJoe's user avatar
1 vote
4 answers
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Is the reason for a stack to decrease the size of a program (by adding the use of subroutines)?

The stack allows subroutines to be used. It can store return address for "return from subroutine" instruction (RTN) and also arguments for the function. It is not possible to store return ...
BipedalJoe's user avatar
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2 answers
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Are variables stored again in RAM?

Assuming this set of instructions: declare variable 'A' which has value 5 declare variable 'B' which has value 2 From what I've understood, those instructions are loaded into RAM an then read by CPU,...
Marshall's user avatar
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2 answers
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What is the most critical component of a processor? [closed]

We know that there are basically 3 fundamental parts of a processor namely : Control Unit (CU) Arithmetical Logic Unit (ALU) Clock Also we know that they maintain several important and different ...
Dipanjan Das's user avatar
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4 answers
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I need to test the speed of performing arithmetic operations on binary numbers

As part of a college project, I need to compare the speed of arithmetic operations directly in binary on different processors. Example: At what speed will binary addition be performed on an Intel Core ...
Kamil 'Moneta' Pietrzak's user avatar
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2 answers
372 views

If a process needs more RAM, does the Page size simply get bigger or does it get a new page?

Let's say I have a Operating System with 4KB page size, but I need to allocate 8kb of memory for all the variables. Does the Process get new page (second one) or does the current page table simply get ...
Lordoftherings's user avatar
1 vote
2 answers
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What happens in harvard architecture pipelining if cpu needs to write data and fetch data at the same time?

What happens if Operand Fetch and Write Back happen in same cycle?
max steuerman's user avatar

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