Questions tagged [cpu]

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Will learning about integrated circuits, help me be a better computer architect(long-term)?

I do not know if this is the right place to ask this type of question, but here I go, im thinking about learning integrated circuits as part of learning more about computer hardware in general (but ...
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16 views

Preemptive priority scheduling problem with same priority

So if T1(priority 3, arrived first) was preempted it is put back to the runqueue. If there is already T4(priority 3, arrived fourth) inside the runqueue, which one of these two will be handled first?! ...
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Where is the register position in a CPU (real image illustration)?

I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
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26 views

How many clock cycles

Actually it differs from CPU to CPU but it is possible to choose a mainstream CPU technology used in moderate servers or home computers. How many clock cycles it takes to read a file of 50KB from ...
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3answers
88 views

Relation between size of address bus and memory size; memory Segmentation in 8086

My question is related to memory segmentation in 8086. I learnt that, 8086 has a 20 bit address bus. And so it can address 2^20 different addresses. Which means it has an memory size of 2^20, i.e, ...
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Textbook on how processors are actually structured at the circuit level

I am looking for a textbook that helps me understand how basic digital electronic units are used to build complicated integrated circuits. I have looked online for textbooks, but what I have found ...
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1answer
19 views

When does kernel accessing virtual memory cause problems

I'm working with the CPU Pintos and have a question that is: In which situations can the kernel accessing the data in virtual memory via a pointer lead to problems? And how do you avoid them? I know ...
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38 views

How to learn how CPU works in details

I've watched multiple videos and read posts regarding modern cpus and how they work. However, those ones very rarely touch the problem on the very basic level. Like I've read about transistors and ...
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1answer
13 views

Neural branch predictors linear, classical predictors exponential, in resources?

Wikipedia states: The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource ...
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1answer
51 views

Information theory of instruction set architecture design?

Information theory to a large extent deals with how to efficiently encode messages given a probability distribution over messages. Intuitively, it seems like we can think of machine instructions (or ...
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1answer
21 views

Reactiveness, cpu and caches

I was messing around with a reactive-based frameworks and found it very expressive. Unfortunately, most of them are using techniques that are not very efficient on CPU cashing mechanism such as ...
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81 views

Advantages of Preemptive Scheduling

I'm currently studying for an exam which includes operating systems. I'm solving the exams from previous years and I'm stuck on a particular question: "One of the advantages of preemptive scheduling ...
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13 views

Direct mapped cache example

i am really confused on the topic Direct Mapped Cache i've been looking around for an example with a good explanation and it's making me more confused then ever. For example: I have 2048 byte ...
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37 views

A microkernel fully hardcoded in hardware?

Does there exist a (micro-)kernel of an operating system that is fully implemented in hardware? That is, a kernel that is not stored in RAM, and loaded into CPU registers after an interrupt or system ...
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88 views

Deep pipeline - cpu architecture

I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance. While reading about vector instruction, I encountered the term deep ...
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2answers
22 views

How to make single cycle processor pipelined?

I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design. I suppose, that I should answer that what should be changed on ...
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1answer
31 views

What happens with register usage in deeply nested functions calls (in theory)?

I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
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85 views

How many registers does a computer *need*?

I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
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65 views

Why no context switch is required in case of spinlock in operating systems?

I have a query regarding the fact that how Spinlocks are advantageous in terms of context switching ?
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2answers
36 views

Why does cpu benchmark increases faster than cpu frequency?

Since duration of an instruction is just the number of cpu cycles needed times the time of a cycle, which is the inverse of the frequency, I do not get why the ratio of cpu benchmark of a two ...
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What is a GPU year?

I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years". What is a GPU year? How long is that?
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If the CPU lowers its speed to the internal clock speed to receive data from RAM, what do RAM speeds influence?

When talking about ram speeds, is it talking about transfer to the CPU? Does the CPU lower its clock speed to the base system clock or to the RAM speeds? Is this why only some RAM speeds are supported?...
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Why the multiplier and quotients can not store in the ACC?

When I study the Arithmetic Unit, there is the below information: there I have some questions: Why the multiplier must store in the MQ and the product must divide ...
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25 views

Is the control bus “measured” in the number of bits it have?

In the system bus, the data bus and the address bus are "measured" in the number of bits that they have, for example we may say that the data bus is 32-bit and the address bus is 32-bit for some CPU ...
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30 views

Map a 16Bits to 32 bits address

So, I'm working on a 16 bits CPU Emulator with these settings: Instructions are 4 Bytes long; 24 bits of an instruction are for data purposes, but only 16 bits are used for memory addressing. All ...
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In Tomasulo's algorithm, how do reservation stations recognise which results are directed to them, especially where functional units are pipelined?

I am currently researching instruction level parallelism in CPUs and have come across Tomasulo's algorithm for dynamic scheduling. As I understand it so far, once a functional unit computes a result,...
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2answers
143 views

How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
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709 views

Confusion in speed up calculation for pipeline architecture

This is an online question I am trying to solve. You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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50 views

Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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3answers
242 views

Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
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1answer
3k views

How to calculate average waiting time for round robin cpu scheduling?

I have tried to calculate average waiting time for the below details there are two answers I'm getting using two methods I'm not understanding which one is correct? The time quantum is 2 This is the ...
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2answers
121 views

Could all CPU instructions get fundamentally faster if a better multiplication method was developed

I was reading the article Integer multiplication in time O(n log n) by David Harvey and Joris Van Der Hoeven, 2019. Could this discovery increase the throughput of future CPU's? If so could we ...
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4answers
105 views

Compiler instructions to sync core caches: are they really needed?

I have read reviews of this book, and quote the following from one of the reviews (emphasis mine): Other than straining your eyes with old-styled C++, you can read such misconceptions in the book ...
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2answers
327 views

What architectural features will allow this microprocessor to access a separate “I/O space”?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition): Consider a hypothetical microprocessor generating a 16-bit address (e.g., ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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23 views

Propagation delay vs max frequency

Do you agree with the following computation - and if no, can you explain why ?, if we make the assumption the the size of a CPU chip is 1 [cm] (which I am not sure, but I guess is not much bigger?): ...
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1answer
65 views

How does the cpu know which process to wake?

In general, my understanding is: the cpu is executing a process/thread until either it is interrupted, the scheduler kicks it out, or it's waiting for something else (I/O for example), when it's put ...
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1answer
73 views

Which unit (control unite or logic unit) issue instructions of load/store?

I learned that the CPU is composed of two units and the machine’s instructions can be categorized into three groupings: (1) the data transfer group, (2) the ­arithmetic/logic group, and (3) the ...
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1answer
73 views

How are words assigned in machine language?

So, if you have an 8-bit computer and it can perform a fetch cycle, meaning it can access its memory, how do you create words the computer understands. If LDA "load the accumulator" is in the ...
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1answer
16 views

multithreading - duration of jobs

" How long will it take for 2 jobs to complete if they're running in parallel, knowing that both have a total of 20 minutes of CPU usage time and 50% IO" I calculated the CPU usage: ...
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1answer
63 views

ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
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1answer
45 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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Who decides that process needs cpu time or not?

I wonder how does particular process gets CPU time or resources whenever it's required to execute some instructions? When a process is in the idle state or waiting for input, it's not occupying the ...
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22 views

How Does an Operating System/BIOS Determine Physical Addresses of Devices?

So I understand that in every computer, the Operating System, the BIOS, or both will determine the physical addresses of the hardware devices and then translate that into virtual addresses. What I don'...
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1answer
384 views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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1answer
80 views

Any CPUs using value prediction, dynamic instruction reuse?

There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
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157 views

Bytes addressable processor

In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
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Does each assembly language correspond to one instruction-set-architecture?

This is a quote from wikipedia: Each computer architecture has its own machine language. Computers differ in the number and type of operations they support, in the different sizes and numbers of ...
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1answer
28 views

Registers in a CPU

https://en.wikipedia.org/wiki/Processor_register So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
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Do most computational efficiency increases due to increased transistor count in the last 70 years depend on some kind of parallelism?

Modern personal computers as far as I understand have increased in power (measured informally by ability to compute “more demanding programs”) due to two “broad factors”: decreased transistor size (...