Questions tagged [cpu]

CPU, stands for Central Processing Unit. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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Can a single core processor be MIMD?

I was wondering for if a single core processor can be MIMD? or MISD? or SIMD? I thought MIMD's requirement is multicore, but I am not sure about this
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What may be the reason for CPU to hang in reset state?

After Firmware loading, CPU enters soft reset state and hangs in there. What may be the reason for this ?
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How do computers *really* work? (at the most basic level)

While learning about computers I will read about RAM and Storage and the CPU, and while these explain the architecture of a computer and how parts of a computer work together, I still don't understand ...
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About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor. We do assume that ...
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Metrics on which Clock Cycles Per Instruction(CPI) depends

In the book - Computer Organization and Design: The Hardware/Software Interface [RISC-V Edition] by Patterson and Hennessy, CPI is defined like this: The term clock cycles per instruction, which is ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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Computer Architecture: How does the parallel prefix adder speed up carry generation?

I am confused by how the parallel prefix adder (the one described in this presentation: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf) ...
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How the task is divided between multiple cores to perform in multiprocessing systems?

I am trying to find how single task is divided between two cores? what are the methods makes them work at the same time without interfering with each other?
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Implementation of memory wait state

How is a dynamic length cpu stall implemented in hardware when the cpu is waiting for a memory fetch?
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Conditional branch instruction

How is a conditional branch instruction implemented in hardware? The instruction checks the sign bit, how does it decide to load pc with the branch address or increment pc to the next sequential ...
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What are address shadows?

In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
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Connection of different buses to memory

The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
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What is the theoretical minimum number of “switches” requried to implement a Turing-complete CPU?

Where "switches" are the basic abstract building blocks for logic gates: vacuum tubes, transistors, magnetic relays, or whatever. We're not counting any switches in the RAM or tape drive ...
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Double Write After Write Dependency in out-of-order/in-order executions

What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register. We know we can solve a simple WAW dependency by ...
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How to know the width/size of a IR (Instruction Register)

I am trying to learn more about the CPU in embedded systems. As I am studying I learned that the IR (Instruction Register) is kind of a special register. What I would like to know is how to know the ...
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Under which conditions a given program is deterministic on x86_64 machines?

Given a certain x86_64 "vanilla" binary, without micro-architecture instructions, which can therefore be executed by any x86_64 computer, what are the conditions for the result to be ...
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Can a trend of android phones slowing down after 2-3 years of usage be attributed to the low durability of RISC CPU used in them?

Laptops, PCs (don't consider Apple products here) have processors that are mainly built on x86 and their life cycle is of the order of 5-10 years. Or the frequent changing of smartphones has a ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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What are the advantages of x86 CPUs over ARM?

Now that Apple is switching the MacOS platform to ARM chips, much has been said about the benefits of ARM processors (they save energy, are passively cooled, and the Apple M1 seems to be faster than ...
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If an instruction contains an address, how is it copied to the MAR?

Since the Memory address bus is unidirectional, how is an address copied to the MAR if a previous instruction such as "STO 150" contains an address? STO would store the contents of the ...
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How do windows executables run on both AMD CPUs and Intel CPUs?

Do they contain instructions for both CPUs or do the CPUs have the same instruction set? Assuming they weren't compiled to an intermediate language (although even then, I think the intermediate ...
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Calculating CPU throughput on a single cycle vs multicycle datapath

When calculating the throughput of a CPU, how does it differ when it is implemented with a single cycle datapath versus a multicycle datapath? If for example the CPU is running 1 GHz freq, then ...
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If the integer representation used is “0 through 4,294,967,295 (2^32 − 1)”, so does this mean the register cannot handle negative numbers?

From Wikipedia: A 32-bit register can store 2^32 different values. The range of integer values that can be stored in 32 bits depends on the integer representation used. With the two most common ...
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Is it wrong to say that the word size of the 8086 and 8088 was 8 bits because a memory location was 8 bits on both of them?

Is it wrong to say that the word size of the 8086 and 8088 was 8 bits because a memory location was 8 bits on both of them? From what I understand that the 8086 and 8088 had a 20 bit memory bus, 16 ...
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What roadblocks are there to HSA becoming standard, similar to floating point units becoming standard?

I remember when my dad explained to me for the first time how a certain model of computer he had came with a "math coprocessor" which made certain math operations much faster than if they ...
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CPU overused vs RAM normal usage, RAM overused vs CPU normal usage

I got asked this question in an interview, where they showed me graphs of CPU being overused and RAM being normally used, and graphs of vice versa. What deductions can we make from this, and how can ...
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What course in CS deals with the study of RAM, CPU, Storage?

I watched the Crash Course playlist of Computer Science. It was teaching about RAM, CPU, Storage etc but I felt it was way too fast and only people who have studied the course first hand understood it ...
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Building an ALU on nandgame's website

I'm working on nandgame's website found here. I'm working on the ALU and here is an image of my implementation: My Implementation: And I compared it to this website's solution: Solution However when ...
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How does the Fetch-Decode-Execute-Reset (FDER) cycle work?

How is this different to the Fetch-decode-execute (FDE) cycle? I have an understanding of the FDE cycle and how the CPU works, although I came across a FDER cycle, when reading about the CPU ...
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
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Is address bus size same as physical address size and is that the same as word size?

I am having some confusion between address bus size, physical address size and word size however (I do understand that unit of memory access is word and when word size is one byte then it's known as ...
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How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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How is CPU different from GPU?

A central processing unit offers to handle various operations like calculating, watching movies, making presentation etc. While a graphics processing unit is majorly used for the purpose of video ...
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What are the differences between Earliest Deadline First (EDF) and Earliest Due Date (EDD)?

From my understanding, the EDF (Earliest Deadline First) rule is essentially an iterative "version" of the EDD (Earliest Due Date) rule, which allows for preemption. At every point in time, ...
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Cores, threads and sockets: what does it mean the calculation $T = tcs$ and the number on windows task manager performance?

Well, suppose then we have an CPU system such as: Thread(s) per core $\equiv t$ : 4 Core(s) per socket $\equiv c$: 4 Socket(s) $\equiv s$: 1 Then, we must to perform a simple ...
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Is x86-64 is just an alias of EM64T?

I was reading a book which describes a historical perspective: Pentium 4E (2004, 125 M transistors). Added hyperthreading, a method to run two programs simultaneously on a single processor, as well ...
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What subfields in computer sciences may one study without learning Object Oriented Programming?

What subfields in computer sciences may one study without learning Object Oriented Programming or is there some kind of degree in Computer Science without the OOP knowledge requirement? Is there a ...
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CPU Registers and Computation

How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit? For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
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modeling DNS server CPU utilization on simulator framework

I'm creating my simulation framework, the DNS system. I have two related questions about the name server. I would like to know how much time the Authoritative Name server spends time to resolve one ...
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How are replacement policies implemented?

Suppose there is a set-associative cache using LRU or ARC replacement policy. What implements these policies? Is it a hardware module or is there a soft doing this?
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Help with performance and speed-up question related to number of cores and their areas

There is a question in my exam that said: Consider the following three processors (x, y, and z) that are all of varying areas. Assume that the single-thread performance of a core increases with the ...
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Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the architecture most likely to have?

Working through some material on CPU architecture and am unsure on the following question: Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the ...
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Are interrupts only found in BIOS?

I may be misunderstanding here-- but are interrupts only found in BIOS and not UEFI systems? More context: "Through standardized calls to the BIOS (“interrupts” in computer parlance), the operating ...
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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
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Preemptive priority scheduling problem with same priority

So if T1(priority 3, arrived first) was preempted it is put back to the runqueue. If there is already T4(priority 3, arrived fourth) inside the runqueue, which one of these two will be handled first?! ...
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Where is the register position in a CPU (real image illustration)?

I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
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How many clock cycles

Actually it differs from CPU to CPU but it is possible to choose a mainstream CPU technology used in moderate servers or home computers. How many clock cycles it takes to read a file of 50KB from ...
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Relation between size of address bus and memory size; memory Segmentation in 8086

My question is related to memory segmentation in 8086. I learnt that, 8086 has a 20 bit address bus. And so it can address 2^20 different addresses. Which means it has an memory size of 2^20, i.e, ...

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