Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
1 vote
3 answers
524 views

Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
2 votes
1 answer
952 views

Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
1 vote
1 answer
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How to determine offset bits when addressing CPU cache?

I know that the offset is based off of the line size for a cache. I have seen the example: "32-btye line size would use the last 5-bits (i.e. 25) off the address as the offset into the line" ...
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2 answers
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How many words of memory map to the same cache entry?

I am going over some practice questions for the Major field exam and it asks: A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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Direct-Mapped cache for Multicore Processor using MSI Protocol

I am reading a case study for Computer architecture, A Quantitative Approach 5th Edition. For reference, I am looking at the case study #1 in Chapter 5 and none of it is making any sense. It says: ...
1 vote
1 answer
8k views

Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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Strides of array and their relation to temporal and spacial locality

I'm really having trouble understanding strides of arrays, and how they relate to temporal and spatial locality in general. I was hoping I could get some help understanding it here. I have the ...
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CPU cache sets and address bits

I have some questions about CPU caches I would like some clarification on. Assume that I have a 128 KB cache with a block size of 64. It is 4-way associative. How many sets does the cache have? How ...
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1 answer
709 views

Direct and Associate Cache - Offset, Index, and Tag

I have two questions: ...
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How to decide row / column strides for a loop over a matrix get these cache hit rates?

Given CPU with: L1 cache: 4-ways, block size = 32 bytes , cache size = 64KB , LRU (Cache replacement policy). L2 cache: 2-ways, block size = 32 bytes , cache size = 512KB , LRU (Cache replacement ...
2 votes
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Von Neumann mixed with Havard in modern CPU?

Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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Performance of CPU with two caches

I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this Cache L1 ...
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Minimum bitrate of common bus (I/O system) with minimum delay

I have a 32-bit MIPS which is connected to the main memory and a I/O system which is related to memory-mapped I/O, while there is DMA controller. The I/O system has discrete I/O communication lines ...
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1 answer
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Are sample memory access traces/dumps available, and where?

I am looking for a realistic physical memory access trace/dump of significant, but not insane, length (on the order of 1M accesses) for the purpose of cache simulation. Preferably for a 16-bit or 32-...
-3 votes
1 answer
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8085 microprocessor connection of CPU data bus with RAM data bus

What would happen if the CPU data-bus bit 2 is connected to the RAM data-bit 5 and CPU data-bus bit 5 is connected to RAM data bit 2? Assume the rest of the connections are all right – explain.
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Where does tag directory is stored

I am studying direct mapping in cache. I understood the concepts like dividing into blocks and lines , tag directory etc. When solving numerical problems of finding main memory size or tag directory ...
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3 answers
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What is a cache write miss?

I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393; The other key ...
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1 answer
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How can an instruction be fetched every cycle?

From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
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3 answers
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Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
10 votes
2 answers
54k views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
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1 answer
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity

Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
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2 answers
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Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Cache/RAM transfer time

I'm studying computer memory and I can't understand the following thing. In a computer architecture is correct to assume that the access time to a word is equal to the transfer time of that word? I'm ...
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1 answer
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What uses have been proposed for overlaid skewed associativity?

In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
2 votes
1 answer
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How does software prefetching work with in order processors?

From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching: ...
1 vote
1 answer
653 views

What does "associative" exactly mean in "n-way set-associative cache"?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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Cache memory temporal locality and spatial locality principles

How does cache memory take advantage of both temporal locality and spatial locality principles?
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How could one construct a TLB so that not all the bits of the presented address need match to result in a hit?

I was wondering besides the typical matching of all bits in the presented address to the resulting page, is there another way of doing so? what are the benefits/ cons and how would one go about doing ...
-2 votes
1 answer
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Find main memory location in cache(direct mapping)

Consider main memory of the size 64 kB with each word being 8 bits(one byte) only and a direct mapping Cache memory of size 4 kB also having data word size 8 bits. Find the following : Find the size ...
2 votes
1 answer
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
1 vote
1 answer
485 views

Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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3 answers
752 views

Loading a word from byte-addressable cache

I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead.. So, my question is pretty much the same as the one in the question I ...
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1 answer
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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1 answer
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Cache read controller

Does the cpu interface with a memory controller to read the cache? What happens when data is not in the cache, a cache miss, does it automatically fetch the data?
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2 answers
7k views

Does the aliasing problem show up in a virtually indexed physically tagged cache?

Basically, and as a simple method, we can access cache with Physical Address which is from the TLB. But, as another method, we can access cache with Virtual Address. But, in this case, if the cache ...
5 votes
3 answers
981 views

Depth first or breadth first ordering in binary search trees?

Let's say that I make a binary search tree and store it in an array so that I end up with an array that is more cache friendly to binary search compared to a sorted array. The binary tree is full on ...
1 vote
2 answers
231 views

In cache-oblivious algorithms, how is recursive reduction of data performed?

From wikipedia: "Typically, a cache-oblivious algorithm works by a recursive divide and conquer algorithm, where the problem is divided into smaller and smaller subproblems. Eventually, one reaches a ...
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Calculating the set field of associative cache

In this example: Assume a system’s memory has 128M words. Blocks are 64 words in length and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set ...
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How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
4 votes
2 answers
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Cache effective access time calculation

In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
1 vote
1 answer
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Cache Miss and Processor Speed

today in my class my professor mentioned that Cache misses becomes more expensive as the speed of the processor increases But he didn't explain the reason. I ...
1 vote
1 answer
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How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
2 votes
3 answers
783 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
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1 answer
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Computing average access time

A computer has a cache memory and a main memory with the following features: - Memory cache access time: 4 ns - Main memory access time: 80 ns - The time ...
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1 answer
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Virtual Memory vs Cache for block identification

Both are based on the principle of locality. Then why virtual memory uses table lookup while cache memory uses associative memory for block identification?
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Cache write misses

I've been using Intel Pin tool to perform analysis of cache miss rates of a parallel application in multi-level caches, using one of the examples allcache.cpp, the results differentiate load and write ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...

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