Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS kernels....
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Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
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Through how many levels must cache writeback propagate?

Suppose that my multicore computer system has the diagrammed memory caches. ...
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Write-To-Read Relaxation in Cache Consistency

Write-to-Read Relaxation means that for a processor: later reads can bypass earlier writes But what does that mean? What exactly is the difference between a read and a write for a Cache? An ...
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Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
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Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
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Determine interference factors in parallel computing

Parallel processes interfere with each other in many ways, by competing for shared resources such as shared caches, memory, disks, etc. Would it be possible to determine latent factors just with a ...
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How to determine offset bits when addressing CPU cache?

I know that the offset is based off of the line size for a cache. I have seen the example: "32-btye line size would use the last 5-bits (i.e. 25) off the address as the offset into the line" ...
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How could one construct a TLB so that not all the bits of the presented address need match to result in a hit?

I was wondering besides the typical matching of all bits in the presented address to the resulting page, is there another way of doing so? what are the benefits/ cons and how would one go about doing ...
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273 views

Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
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Cache write misses

I've been using Intel Pin tool to perform analysis of cache miss rates of a parallel application in multi-level caches, using one of the examples allcache.cpp, the results differentiate load and write ...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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Calculating miss rate for 2 way set associative cache

From my homework: Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is ...
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Cache Hit or miss

Asume 512 Bytes direct-mapped cache with 64 Byte cache blocks (cache line size), is empty at the beginning and below given set of physical addresses are referred by CPU in the given order. At each ...
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Set Associative Cache Exercises

I am trying to solve an exercise on set-associative cache , i struggled with it for a while but i think that i figured out the answer , would be helpful if someone could check if my solution is ...
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MESI protocol and write to Main Memory

I am studying cache coherence MESI protocol with "intervention" (cache can send to other cache without use the Main Memory). On my notes I wrote that in case of a processor has a block in M (modified ...
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Physically indexed virtually tagged cache

PIVT cache is indexed physically so address translation using TLB is needed to get into cache and we use virtual address as the tag for comparison . I read that homonym is a problem which is caused ...
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Principle of locality for object-key data pairs

It seems that if we only have object-key cache then we won't have spatial locality and only temporal locality. I use memcached in a python application and that has only object-key pairs and no ...
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Picking Block Size in Caches

How does one pick an optimal block size for a cache with a specific size limit? For example, if I have a size limit of 900 bits for the whole cache, including tags and validity bits and everything, ...
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Understanding a Computer Architecture Problem

Below, we have given you four different sequences of addresses generated by a program running on a processor with a data cache. Cache hit ratio for each sequence is also shown below. \begin{...
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2-way set associative mapping Hit or Miss

I've been trying to find out how to determine Hit or Miss regarding this info: 2-Way Set associative cache memory which contains 32 blocks with 4 bytes in each block, Accesses were done to addresses ...
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8085 microprocessor connection of CPU data bus with RAM data bus

What would happen if the CPU data-bus bit 2 is connected to the RAM data-bit 5 and CPU data-bus bit 5 is connected to RAM data bit 2? Assume the rest of the connections are all right – explain.
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Cache/RAM transfer time

I'm studying computer memory and I can't understand the following thing. In a computer architecture is correct to assume that the access time to a word is equal to the transfer time of that word? I'm ...
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How does changing cache size and/or block size affect the hit rate of the for loops in the following code?

I am working on practice problems to study for an upcoming exam. I am given the following piece of code: ...
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Double Write After Write Dependency in out-of-order/in-order executions

What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register. We know we can solve a simple WAW dependency by ...
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Cache Direct Map access confusion

Ok, I've found a good example But it doesn't really answer my question. Simple Example We have a 8 two-word blocks. So we have an offset of 1 bit. Say we have two references 33 and 32. ...
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Functionning of the eviction set for Prime and Probe

I have to write a report about Prime and Probe, more specifically about its eviction set method, and there are two notions that remain blurry for me : To find the set, we use huge pages like it's ...
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Help understanding main memory to cache block mapping

I'm currently self-learning on the cache memory and have come across a method on how to find out which cache block a memory address will be mapped to: ...
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Hardware implementation of direct mapped , set associative mapped and fully associative cache

I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
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I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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64 byte cache block and memory overhead for cachline with 7 states (3 bits)

I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead: The cache line has 7 states (3 bits): unowned, shared, exclusive, ...
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Associative mapped cache, word addressable

I have an associative mapped cache with 10 tag bits and an offset of 7bits. What is the size of each main memory block in words(word addressable) and main memory size in words? i worked it out as: ...
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Cache mapping calculation

A cache has following specifications: Block size = 16 Bytes Set size = 2 way set associative Number of sets = 128 Physical address = 23 bits, byte addressable My Questions are: 1) How many blocks ...
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Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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1answer
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Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
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Cache mapping problem

Okay.I have problem about cache mapping. Here is the problem . Memory size is 1 MB Byte addresable Cache block size is 16 Bytes. Cache size is 64kb Since memory is 1 mb=2**20 Bytes. So we need ...
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Computer Architecture: Hit ratio with address

There is a problem that as much as I am trying to understand it, I fail. There are theoretically three cache manufacturers that each make 16 byte cache. The first has 16 blocks, 8 blocks the second, ...
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Trouble with Direct Mapping for Caches

I have an online homework assignment that is asking me for the tag and index in a direct-mapped cache, for a series of memory addresses. The cache is specified to have 16 one word blocks. One of the ...
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How to find number of blocks in cache?

Suppose a computer using direct mapped cache has 512KB of main memory and a cache of 4 Bytes, where each cache size is 64KB. 1)Find Number of blocks in cache.
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How is there a CPU read misses on exclusive caches?

If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive. It is exclusive because it is only there. How can there be ...
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Which of the following cache designer guidelines are generally valid?

Which of the following cache designer guidelines are generally valid? The shorter the memory latency, the smaller the cache block The shorter the memory latency, the larger the cache block The higher ...
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Direct-mapping cache question

Say I have the following memory scheme: Data bus: 8 bit Main Memory Store: 256 Byte Cache Store : 32 Byte Block Size : 4 Byte How would I go about listing the assigned bits for tag,...
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Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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Cache calculation

My question is fairly simple, however I am not entirely sure if my solution is correct. In this case we are using direct mapping. I know the value of byte-addressable memory and I know the block size ...