Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Two addresses point to the same data - is the data then stored 2 times in the cache?

Let's say a program reads the addresses 0x00 cd 10 54and0x00 cd 10 50. The tag size and and index size added are just 4 bits, ...
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Calculating the set field of associative cache

In this example: Assume a system’s memory has 128M words. Blocks are 64 words in length and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set ...
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Does the aliasing problem show up in a virtually indexed physically tagged cache?

Basically, and as a simple method, we can access cache with Physical Address which is from the TLB. But, as another method, we can access cache with Virtual Address. But, in this case, if the cache ...
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What determines a hit or a miss for direct mapped cache?

I've been stuck on this for a while now, I've tried reading the related topics on cs.stackexchange as well as the textbook and youtube videos. Suppose we have a 8KB direct-mapped data cache with 64-...
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Direct-mapping cache question

Say I have the following memory scheme: Data bus: 8 bit Main Memory Store: 256 Byte Cache Store : 32 Byte Block Size : 4 Byte How would I go about listing the assigned bits for tag,...
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Associativity vs blocks per set in fixed size caches

I am trying to understand the following claim: For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i.e., the number or ways) and ...
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Total number of bits of storage for direct mapped cache

I have a homework assignment dealing with caches. We are asked to compute the total number of bits of storage required for the cache, including tags and valid bits. Then compute the overhead for the ...
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Picking Block Size in Caches

How does one pick an optimal block size for a cache with a specific size limit? For example, if I have a size limit of 900 bits for the whole cache, including tags and validity bits and everything, ...
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Direct-mapping cache

I had this question on a previous homework assignment and was unable to answer it. I've done some research and am not really able to find anything that clears this up for me. Would appreciate any help ...
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Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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Spinlock using cache coherence

Have been trying to understand the image below which shows status of spinlock using cache coherence. Reference is Computer Architecture A Quantitative Approach------------------ Could anybody explain ...
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Cache calculation

My question is fairly simple, however I am not entirely sure if my solution is correct. In this case we are using direct mapping. I know the value of byte-addressable memory and I know the block size ...
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Write Serialization for Cache Coherence in the presence of Store Buffers

One of the requirements for a coherent memory system is write serialization - "two writes to address X by any two processors are observed in the same order by all processors". I am not sure how this ...
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Understanding a Computer Architecture Problem

Below, we have given you four different sequences of addresses generated by a program running on a processor with a data cache. Cache hit ratio for each sequence is also shown below. \begin{...
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Direct Mapped, Cache Transactions

I have attached the problem below Consider a 512-KByte cache with 64-word cachelines (a cacheline is also known as a cache block, each word is 4-Bytes). This cache uses write-back scheme, and the ...
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Understanding Cache Mapping and Access (Computer Architecture)

Consider a 512-KByte cache with 64-word cachelines (a cacheline is also known as a cache block, each word is 4-Bytes). This cache uses write-back scheme, and the address is 32 bits wide. Answer the ...
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Why register access bandwidth is higher then residing inside CPU cache?

Access to registers claimed to be faster then cache. Why is it? Is it because cache has less wires or spatially further from functional units?
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If direct mapping scheme was used instead what will be the size of the tag field?

A computer has a 32K main memory and a 4K fully associative cache memory. The block size is 8 words. The access time for main memory is 10 times that of main memory. a. What is the size of tag field ...
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Can someone give me an explanation of how dcaches works?

So, I'm trying to do a computer architecture assignment and there's a question about dcaches. Here's the question: Given a 16 word dcache initially filled with word address 0, 1, 2, …15 memory ...
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Can the cache always miss while trying to write to the cache?

According to the lecture, a virtual address first goes to the TLB. If the TLB hits, it is then checked, if something has to be either read or written from cache. In case of writing, it is then ...
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Why do we ignore the significant digit for 2-word and 2 significant digit for 4-word?

Imagine there are 3 direct-mapped cache designs possible, all with total 8-words of data: C1 has 1-word, C2 has 2 -words block, and C3 has 4-word blocks. Assume the sequence of memory accesses is 3,...
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Tag, Index, offset for 3 different Direct-mapped cache design

This is related to an question asked and answered already, but I thought it was better to open a new question than necro a 1+ year old topic. Below is a list of 32-bit memory address references, ...
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Mapping an address to a cache block

A cache with 64 blocks(block0 to block63) and each block of size 16 bytes (or 4 words). This is what I think of the address arrangement, if it is byte addressable. block0 has addresses: 0, 64, 64*...
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Fully associative cache - calculate address tag bits?

I have the following task: Main memory capacity = 64MB (B = byte) Cache capacity = 64KB Block size = 16B Processor addressed information with address A = 0052A622h Calculate address tag ...
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Basic question about 4-way set associative

When the CPU writes or reads from the memory and stores the value that was read or written into L1 cache. Do the CPU store the whole block( 1 block , leaves the other three ways empty) or the whole ...
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2-way set associative mapping Hit or Miss

I've been trying to find out how to determine Hit or Miss regarding this info: 2-Way Set associative cache memory which contains 32 blocks with 4 bytes in each block, Accesses were done to addresses ...
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How do stack-based cache algorithms avoid Belady's anomaly?

I was going through page replacement algorithms from Galvin's Operating System book. I encountered this line about LRU: A stack algorithm is one in which the pages kept in memory for a frame set ...
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Pros and Cons of Average Memory Access Time When Increasing Cache Block Size

Assuming we have a single-level (L1) cache and main memory, what are some of the advantages and disadvantages of having a larger cache block size (considering average memory access time). The only ...
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Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
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Miss penalty for Write request in a Write-Back style system

If the processor is trying to write a word to a certain memory location, and the system uses a write-back style architecture, what happens in case of a miss? I'm assuming that the system would first ...
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Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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Computing the hit and miss ratio of a cache organized as either direct mapped or two-way associative

This is an example problem in a computer organization and architecture course that's giving me some trouble. It goes as follows: Consider a cache of 4 lines of 16 bytes each. Main memory is divided ...
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Hashtable vs cache-oblivious

This question has been asked in the theoretical community, but deemed as too practical. I am moving it here, I hope it is on-topic. I'd like to know more about real performances of data structures, ...
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How is parallel tag checking achieved in associative Mapping?

I originally posted this question on stack overflow and then realised it was better suited to computer science . In the book on computer organization and architecture by William stallings , in the ...
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Why is quiescent consistency compositional, but sequential consistency is not

I'm having trouble in comparing these two memory consistency models. Essentially for sequential consistency I think of real code like this: ...
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Difference between capacity miss and conflict miss

Premise: Two types of cache miss: capacity miss, conflict miss\ Cache contains only 2 sets, SET 1 and SET 2 Problem: If data A maps to SET 1 and it doesn't exist in SET 1 while SET 1 is fully ...
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Performance on modifying cycle time

I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is ...
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What's the difference between clock replacement & LRU replacement?

As title. When we want to request following page numbers 2,4,4,2,5,2,1,1,3,1, is clock replacement better? What are the advantages and disadvantages of them? Thanks~
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How to compute $\mathbf{X}^T \mathbf{X}$ efficiently for large $\mathbf{X}$?

Let $\mathbf{X}$ be a $n \times n$ matrix. Given that we can only keep $k$ rows ($k << n$) or columns of the matrix in memory, how can we compute $\mathbf{X}^T \mathbf{X}$ while minimizing the ...
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Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
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Why do caches fetch data to the right if the offset bit is 0 and to the left if it is 1 in a 2-word block

Here is an example of table with 32 bit addresses and their respective indexes and tags. The cache has a total of 8 blocks and 2-word blocks. So since we have 2 word blocks, that means that the ...
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Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
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Know when we have a cache default and if it loads

I have an exercise about cache memory, first the cache is empty : I have a cache memory with 16 lines and each lines have 16 octet, the address is 16 bits So I know that the INDEX will be composed of ...
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Direct mapping cache with LRU

I'm studying computer architecture and I'm doing an experiment. Does LRU make sense in a direct mapping cache? I'm quite confused. Thank you.
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Depth first or breadth first ordering in binary search trees?

Let's say that I make a binary search tree and store it in an array so that I end up with an array that is more cache friendly to binary search compared to a sorted array. The binary tree is full on ...
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Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

Does having one larger L1 cache instead of L1 and L2 cache makes computation faster? Also will this make the CPU more expensive to make?
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In a $k$-way set associative cache,main memory block mapping in range?

In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are ...
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Caches and reading a PDF

I am currently learning about caches in Systems class, and I had a few doubts about what exactly happens when a Computer reads a PDF. This is the sequence that happens in my mind: The CPU checks if ...
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How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
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What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...