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Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Through how many levels must cache writeback propagate?

Suppose that my multicore computer system has the diagrammed memory caches. ...
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Why page size = size of one cache way?

Why is that the page size equals the size of one cache way? My book states "A direct-mapped cache cannot be bigger than a page".
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Physically indexed virtually tagged cache

PIVT cache is indexed physically so address translation using TLB is needed to get into cache and we use virtual address as the tag for comparison . I read that homonym is a problem which is caused ...
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What is the difference between caching, buffering and paging? Expecting a detailed answer on the OS level

I have been reading about caching and buffering it seems about the same to me can't get hold of the differences clearly and paging, for now the only difference I understand between paging and caching ...
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CPU cache - retrieving data from memory

Regarding CPU cache, if the CPU does not find the data it needs in the cache, I understand it then looks for it in the main memory (RAM). (Let's assume we have only one level of cache in order to keep ...
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Hit/Miss in a 2-way set associative cache with offset

"In a 2-way set associative cache of 4 blocks containing 4 words each, which one of these addresses will return a hit when being read? The blocks to be retained in the cache are decided by LRU." 4 ...
hav000ookk's user avatar
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What is Memory Mapping in Cache?

People all over the internet are asking "What are the different Memory Mapping Techniques in Cache", but i couldn't find anywhere the answer to "What is Memory Mapping exactly?". Please tell what do ...
sb-coder's user avatar
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Calculate Miss rate of L2 cache given global and L1 miss rates

If I have a Global miss rate of all caches of a total of 5.41% and the miss rate of a single level cache of 9.13%, how can I effectively calculate how much the second level cache miss rate need to be? ...
Rick's user avatar
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how os can calculate cpu cache size?

There's an interview question. In my opinion, os can calculate cache hit rate and miss rate(with the total running time of process and the number of transfer of block of memory to cache). But how can ...
A.Cho's user avatar
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Which of the following cache designer guidelines are generally valid?

Which of the following cache designer guidelines are generally valid? The shorter the memory latency, the smaller the cache block The shorter the memory latency, the larger the cache block The higher ...
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Calculating fractions of accesses from various levels of memory? (L2 - Main)

I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer. The question goes; ...
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Principle of locality for object-key data pairs

It seems that if we only have object-key cache then we won't have spatial locality and only temporal locality. I use memcached in a python application and that has only object-key pairs and no ...
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Computing the size of an m-associative cache

I am trying to answer this question: Consider a computer with a byte-addressable memory. A 40-bit memory address is divided as follows for cache processing. First, the 8 low-order bits are chopped ...
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Determine number of blocks in a cache

The question is: We need to design a cache with cache size of 128K bytes, block (line) size of 8 words, and word size of 4 bytes. Consider a computer with 64-bit physical address. The cache is ...
steve's user avatar
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calculate average CPI [closed]

I cannot solve this exercise: "If a processor has a cache hit rate of 99.5% and a cache miss penalty of 160 core processor cycles, what will the average CPI be for 1,000 instructions?" how can i do ...
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Numerical problem on Access time in Cache memory

For a system with two levels of cache, define: $T_{c_1}$ is the first-level cache access time $T_{c_2}$ is the second-level cache access time $T_m$ is the memory access time $H_1$ is the first-level ...
Shivam Tiwari's user avatar
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1 answer
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How would a CPU know if a piece of data is in cache or RAM or on disk?

How would a CPU know if a piece of data is in cache or RAM or on disk? This would imply there's some sort of meta addressing scheme on where everything is.
user3201068's user avatar
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Cache (TLB) - fully associative cache

I have an exercise and I don't understand the solution. ...
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How to calculate the number of tag, index and offset bits of 2 different caches? [closed]

I have two exercises: 1) A 128KB direct-mapped cache, with lines from 32bytes/lines and 36-bit address. 2) A 512KB 2-way associative cache, with lines from 64bytes/lines and 36-bit address. For both ...
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Write-To-Read Relaxation in Cache Consistency

Write-to-Read Relaxation means that for a processor: later reads can bypass earlier writes But what does that mean? What exactly is the difference between a read and a write for a Cache? An ...
Seen's user avatar
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1 answer
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Write through and write back cache policies

There are Two Write Hit policies: Write Through and Write back There are Two Write miss policies: Write Allocate and No Write Allocate There are two memory access techniques: simultaneous and ...
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Two addresses point to the same data - is the data then stored 2 times in the cache?

Let's say a program reads the addresses 0x00 cd 10 54and0x00 cd 10 50. The tag size and and index size added are just 4 bits, ...
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Calculating the set field of associative cache

In this example: Assume a system’s memory has 128M words. Blocks are 64 words in length and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set ...
user3125670's user avatar
9 votes
2 answers
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Does the aliasing problem show up in a virtually indexed physically tagged cache?

Basically, and as a simple method, we can access cache with Physical Address which is from the TLB. But, as another method, we can access cache with Virtual Address. But, in this case, if the cache ...
A.Cho's user avatar
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What determines a hit or a miss for direct mapped cache?

I've been stuck on this for a while now, I've tried reading the related topics on cs.stackexchange as well as the textbook and youtube videos. Suppose we have a 8KB direct-mapped data cache with 64-...
Eric Gumba's user avatar
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Direct-mapping cache question

Say I have the following memory scheme: Data bus: 8 bit Main Memory Store: 256 Byte Cache Store : 32 Byte Block Size : 4 Byte How would I go about listing the assigned bits for tag,...
Callat's user avatar
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2 answers
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Associativity vs blocks per set in fixed size caches

I am trying to understand the following claim: For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i.e., the number or ways) and ...
TheMathNoob's user avatar
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1 answer
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Total number of bits of storage for direct mapped cache

I have a homework assignment dealing with caches. We are asked to compute the total number of bits of storage required for the cache, including tags and valid bits. Then compute the overhead for the ...
Carousser's user avatar
1 vote
0 answers
357 views

Picking Block Size in Caches

How does one pick an optimal block size for a cache with a specific size limit? For example, if I have a size limit of 900 bits for the whole cache, including tags and validity bits and everything, ...
Zach Zundel's user avatar
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1 answer
439 views

Direct-mapping cache

I had this question on a previous homework assignment and was unable to answer it. I've done some research and am not really able to find anything that clears this up for me. Would appreciate any help ...
Ashlee Berry's user avatar
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187 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
Thomas Lee's user avatar
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2 answers
643 views

Spinlock using cache coherence

Have been trying to understand the image below which shows status of spinlock using cache coherence. Reference is Computer Architecture A Quantitative Approach------------------ Could anybody explain ...
Abhishek Dhankar's user avatar
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135 views

Cache calculation

My question is fairly simple, however I am not entirely sure if my solution is correct. In this case we are using direct mapping. I know the value of byte-addressable memory and I know the block size ...
James Arthur's user avatar
8 votes
3 answers
2k views

Write Serialization for Cache Coherence in the presence of Store Buffers

One of the requirements for a coherent memory system is write serialization - "two writes to address X by any two processors are observed in the same order by all processors". I am not sure how this ...
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Understanding a Computer Architecture Problem

Below, we have given you four different sequences of addresses generated by a program running on a processor with a data cache. Cache hit ratio for each sequence is also shown below. \begin{...
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Direct Mapped, Cache Transactions

I have attached the problem below Consider a 512-KByte cache with 64-word cachelines (a cacheline is also known as a cache block, each word is 4-Bytes). This cache uses write-back scheme, and the ...
TheMathNoob's user avatar
1 vote
1 answer
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Understanding Cache Mapping and Access (Computer Architecture)

Consider a 512-KByte cache with 64-word cachelines (a cacheline is also known as a cache block, each word is 4-Bytes). This cache uses write-back scheme, and the address is 32 bits wide. Answer the ...
TheMathNoob's user avatar
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1 answer
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Why register access bandwidth is higher then residing inside CPU cache?

Access to registers claimed to be faster then cache. Why is it? Is it because cache has less wires or spatially further from functional units?
user60990's user avatar
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1 answer
241 views

If direct mapping scheme was used instead what will be the size of the tag field?

A computer has a 32K main memory and a 4K fully associative cache memory. The block size is 8 words. The access time for main memory is 10 times that of main memory. a. What is the size of tag field ...
Mehroz Naqvi's user avatar
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1 answer
123 views

Can someone give me an explanation of how dcaches works?

So, I'm trying to do a computer architecture assignment and there's a question about dcaches. Here's the question: Given a 16 word dcache initially filled with word address 0, 1, 2, …15 memory ...
El Dj's user avatar
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Can the cache always miss while trying to write to the cache?

According to the lecture, a virtual address first goes to the TLB. If the TLB hits, it is then checked, if something has to be either read or written from cache. In case of writing, it is then ...
Imago's user avatar
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Why do we ignore the significant digit for 2-word and 2 significant digit for 4-word?

Imagine there are 3 direct-mapped cache designs possible, all with total 8-words of data: C1 has 1-word, C2 has 2 -words block, and C3 has 4-word blocks. Assume the sequence of memory accesses is 3,...
user58504's user avatar
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Tag, Index, offset for 3 different Direct-mapped cache design

This is related to an question asked and answered already, but I thought it was better to open a new question than necro a 1+ year old topic. Below is a list of 32-bit memory address references, ...
user3605848's user avatar
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1 answer
3k views

Mapping an address to a cache block

A cache with 64 blocks(block0 to block63) and each block of size 16 bytes (or 4 words). This is what I think of the address arrangement, if it is byte addressable. block0 has addresses: 0, 64, 64*...
electronics's user avatar
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409 views

Fully associative cache - calculate address tag bits?

I have the following task: Main memory capacity = 64MB (B = byte) Cache capacity = 64KB Block size = 16B Processor addressed information with address A = 0052A622h Calculate address tag ...
Millkovac's user avatar
1 vote
1 answer
2k views

Basic question about 4-way set associative

When the CPU writes or reads from the memory and stores the value that was read or written into L1 cache. Do the CPU store the whole block( 1 block , leaves the other three ways empty) or the whole ...
bopia's user avatar
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2-way set associative mapping Hit or Miss

I've been trying to find out how to determine Hit or Miss regarding this info: 2-Way Set associative cache memory which contains 32 blocks with 4 bytes in each block, Accesses were done to addresses ...
user3161261's user avatar
3 votes
1 answer
2k views

How do stack-based cache algorithms avoid Belady's anomaly?

I was going through page replacement algorithms from Galvin's Operating System book. I encountered this line about LRU: A stack algorithm is one in which the pages kept in memory for a frame set ...
Maharaj's user avatar
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1 vote
3 answers
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Pros and Cons of Average Memory Access Time When Increasing Cache Block Size

Assuming we have a single-level (L1) cache and main memory, what are some of the advantages and disadvantages of having a larger cache block size (considering average memory access time). The only ...
dmnte's user avatar
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0 votes
2 answers
421 views

Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
Babak Doe's user avatar