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Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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17
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1answer
18k views

Memory Consistency vs Cache Coherence

Is it true that Sequential Consistency is a stronger property than Cache Coherence? According to Sorin, Daniel J; Hill, Mark D; Wood, David A: A Primer on Memory Consistency and Cache Coherence, ...
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2answers
1k views

Owned state in MOESI protocol-transitions?

I understand that MESI is a subset of the MOESI cache coherency protocol. But what does the Owned state in the MOESI protocol represent? What are the differences in state transition due to the extra ...
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2answers
614 views

MESI Protocol Invalid cache line is attempted to be stored?

I am implementing a sample MESI simulator having two levels of cache (write back). I have added MESI status bits to both levels of cache. As it is a write back cache, the cache line is updated to L2 ...
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3answers
677 views

Parallelising random reads seems to work well — why?

Consider the following very simple computer program: for i = 1 to n: y[i] = x[p[i]] Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an $n$-...
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0answers
12k views

What determines a hit/miss with cache memory?

I was taught that when a reference is mapped to a cache block, X, for the first time, the word is stored in the cache block, bearing a tag and index that helps identify it for future reads. Then, ...
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1answer
385 views

In cache addressing, what value is placed in the offset field?

There is a 64 KB 1-word cache, and a word is 32 bits. From that I can derive that the length of the tag field is 16 bits, the length of index field is 14 bits, and, as my professor taught me, there ...
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2answers
217 views

In cache-oblivious algorithms, how is recursive reduction of data performed?

From wikipedia: "Typically, a cache-oblivious algorithm works by a recursive divide and conquer algorithm, where the problem is divided into smaller and smaller subproblems. Eventually, one reaches a ...
15
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1answer
21k views

How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
4
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2answers
754 views

How to avoid column wise access in matrix multiplication?

I know when we access elements in rows it will be much faster than if it is accessed column wise. In matrix multiplication one of the matrices must be accessed column wise. In GPUs with CUDA/OpenCL ...
3
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1answer
2k views

Understanding the basic concepts in memory organisation

(Before actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.) I have recently started ...
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0answers
207 views

Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
4
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1answer
5k views

Performance of row- vs. column-wise matrix traversal

Scott Meyers describes here that traversing a symmetric matrix row-wise performes significantly better over traversing it column-wise - which is also significantly counter-intuitive. The reasoning ...
2
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1answer
3k views

Multi-level cache for which inclusion holds [closed]

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? L1 must be a write-through cache. L2 must be a write-through cache. ...
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5answers
281k views

How to calculate the number of tag, index and offset bits of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
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2answers
653 views

In the "tall cache assumption" what does $\Omega$ represent?

Within the field of cache-oblivious algorithms the ideal cache model is used for determining the cache complexity of an algorithm. One of the assumptions of the ideal cache model is that it models a "...
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1answer
270 views

How many words loaded on a cache miss

Regarding Processor Direct Cache, what is the proper mathematical technique for discovering how many words are loaded on a cache miss? For example if you have a direct mapped cache with a total data ...
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3answers
5k views

Finding cache block transfer time in a 3 level memory system

Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it : A computer system has an L1 cache, an L2 cache, and a main memory unity connected as ...
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2answers
3k views

Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
10
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3answers
3k views

CPU Cache is managed by which software component?

CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
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4answers
1k views

Does the write through cache copies the whole block or just the byte which is updated?

Just a basic question to ask Does the write through cache copies the whole block or just the byte which is updated? I went through the following question Array A contains 256 elements of 4 bytes ...
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2answers
77 views

Cache strategies, what reference article could I study?

So as to optimize an application, I must implement data caching: not to recompute some data - those heavy on cpu but that don't change often. When playing with the idea, I imagined something like the ...
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2answers
11k views

Doubt regarding cache hit ratios and access time

Question 1: What is the average access time for a 3-level memory system with access time $T_1$, $2T_1$ and $3T_1$? (Hit ratio $h_1$ = $h_2$ = 0.9) The solution given is: $0.9[T_1] + 0.1(0.9[2*T_1] + ...
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0answers
100 views

Determine interference factors in parallel computing

Parallel processes interfere with each other in many ways, by competing for shared resources such as shared caches, memory, disks, etc. Would it be possible to determine latent factors just with a ...
6
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1answer
519 views

Why can L3 caches hold only shared blocks?

In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches (e....
61
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2answers
26k views

What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
14
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1answer
380 views

Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
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2answers
2k views

Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...

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