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1answer
23 views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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0answers
45 views

CPU instruction cache miss handling

In short, I'm trying to understand how assembly instructions flow through the simple 5-stage CPU pipeline in MIPS. The problem is that I can't find any decent example how instruction cache miss can be ...
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0answers
25 views

The number of cycles needed to execute the following loop in pipeline processor?

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute ...
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2answers
52 views

Difference between delayed branches and out-of-order execution

I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
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1answer
48 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
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1answer
39 views

Pipeline question

I have this multiple choice question from a computer architecture class, a mips processor executes a program at 10 sec, without pipelining and clock rate 100 MHz. When running the program on a ...
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1answer
19 views

What are the prerequisites for instruction pipelining to work?

When can it be applied? When can it not be used? I get the general idea but not what it takes to make it work.
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1answer
47 views

How is the control unit affected by pipelining? [closed]

Compared to not using instruction pipelining. What is different?
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0answers
39 views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
2
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1answer
52 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
0
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1answer
150 views

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
2
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1answer
41 views

The total time require for a pipeline to execute

The book says that a total time required for a pipeline with k stages to execute n instructions is as follows. $T _{k,n} =[pqnk+(1-pq)(k+n-1)] \tau$ p is the probability of encountering a branch ...
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2answers
36 views

predication execution, branch prediction

Below is a paragraph from a book. In an ordinary superscalar processor, we would use branch prediction to guess which of the given instructions is to be executed, and go down that path. If the ...
1
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1answer
29 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
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0answers
152 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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2answers
256 views

Do unconditional branches cause control hazards?

Do unconditional branches, such as jump/goto instructions cause control hazards? If so, why? I am wondering because if ...
0
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1answer
61 views

How can I make a pipeline with undefined/unlimited stages?

I've been told that if you understand a pipeline then you should be able to make it with any depth, but I can only do 4 stages and maybe 5 if the memory is not too slow. How can I learn how to make ...
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0answers
291 views

Types of pipelining?

if pipelining is devided to polyfunctional pipelining and monofunctional pipelining(im sorry im not a native speaker the name may be incorect) and the polyfunctional pipelining is futher devided to ...
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0answers
127 views

Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
2
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2answers
36 views

Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
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0answers
40 views

What is the impact of locality principles on the pipelining techniques?

I know what are both locality principles and pipelining techniques. But I can't see any sort of interconnection between the two things. How can locality principles impact pipelining techniques?
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2answers
73 views

how long will it take to execute a ten-stage pipeline

Suppose you design a computer with a ten-stage Pipeline to execute one instruction, with each stage taking 5nsec A)how long ...
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0answers
16 views

how long will it take to execute a ten-stage pipeline [duplicate]

Suppose you design a computer with a ten-stage Pipeline to execute one instruction, with each stage taking 5nsec A)how long ...
-3
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1answer
152 views

Execution time of a linear pipeline

A simple linear pipeline has three stages. The execution times in the stages are 10, 15, and 12 units respectively. If the pipeline is used to process 100 inputs, then the execution time is (a)...
0
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1answer
113 views

how one memory can be accessed simultaneously in instruction fetch and data read?

In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel. But datas and instructions are usually in same memory, and their access address is ...
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1answer
1k views

Architecture, microarchitecture and ISA in microprocessor [duplicate]

What is Architecture, microarchitecture and ISA in processor. How do they relate to each other and what is the difference between them. Elucidate their differences with examples so that it is ...
2
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1answer
5k views

What's the difference between dynamic and static pipelines?

I was trying to understand what a reservation table is in the context of pipelining, when I found this reference here, where the author mentions that there are static and dynamic pipelines. According ...
0
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1answer
13 views

which Pipelining architecture, should i use and how to distinguish them!

Is there any specific architecture to pipelining that we must follow to perform "operand-forwarding" inorder to avoid its harzards? My tutor seem to have, there are different architecture. And he ...
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1answer
28 views

Can an instruction with a dependency read the register in same cycle as it's being written?

I'm learning about superscalar processors and struggling with it a bit. I wrote an assembly program and now must move it through in-order in-issue completion and I have a question about instructions ...
3
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1answer
127 views

Branch wrong prediction pipeline

Let's say we have a pipeline with 20 stages. If the testing for the jump condition is done at stage 14 and we have a wrong prediction, then the instructions processed in those 14 stages, that shouldn'...
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0answers
231 views

Pipeline depth with idle stages

To keep througput close to 1/cycle when there is a multi-cycle stage that sends a command to a far module then gets answer(10 clocks per send or receive), could separating it in two(send + receive) ...
1
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2answers
181 views

For data-path cycles in MIPS, what determines wheter a control signal gets the “don't-care” value?

For example for the sw command in MIPs, the control signal values are ALUOp1: 0 ALUOp: 0 RegWrite: 0 MemRead: x MemWrite: 1 Branch: 0 ALUsrc: 1 RegDest: x MemToReg: x Why do memRead, ...
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1answer
2k views

What is the difference between Data Hazard and Dependencies in Pipelining

In my GATE Exam I have given with the following question statements and R5 ← R0 + R1 R6 ← R2 * R5 R5 ← R3 - R6 R6 ← R5/R4 X ← R6 the question was to calculate number of Output,True and Anti ...
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2answers
322 views

Computer architecture pipelining

LOOP:LW R1,0(R2) ADDI R1,R1,#1 SW R1,0(R2) ADDI R2,R2,#4 SUB R4,R3,R2 BNEZ R4, LOOP If we want to move an instruction into a ...
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0answers
33 views

Do add commands in an pipeline wait for each other's result?

Let be given a 4-step pipeline with the steps "Get command, get operands, Execute command, Write back result" and an Assembler Code: ...
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1answer
308 views

Question about branch hazards on 4-stage pipeline

Let's say that conditional branches are resolved at the 2nd-stage on a 4-stage pipeline. Why is there different penalties on a taken branch versus an untaken branch ? Should the penalty be the same ...
1
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1answer
46 views

Basic question about branches and pipelines

In which stage ( on an ideal 5-stage pipeline ) are branches and hazards handled? How much is the branch penalty for a branch hazard or data hazard. Is there different stages to find data hazards or ...
1
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1answer
90 views

RISC machines have register renaming?

I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming? I know that ...
2
votes
1answer
135 views

In instruction pipelining, can we forward an operand more than one clock cycle?

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from ...
2
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1answer
2k views

Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
1
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1answer
120 views

How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y R4 = R2 + X ...
3
votes
1answer
113 views

Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
3
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2answers
113 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
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0answers
124 views

What are exceptions and how they will be raised in pipeline

Hi I am not sure what is exception here and how it will be raised in following case Sub $11,$2,$4 And $12,$2,$5 Or $13, $2,$6 Add $1,$2,$1 Slt $15,$6,$7 I was ...
2
votes
1answer
774 views

Read After Write(RAW) hazard

I am confused in finding RAW dependencies whether we have to find only in adjacent instructions or non-adjacent also. consider the following assembly code I1: ADD R1 , R2, R2; I2: ADD R3, R2, R1; ...
3
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2answers
153 views

Clear interrupt instruction in a pipelined CPU

Say you execute a clear interrupt instruction (CLI) in a pipelined CPU. While that instruction is being fetched, an interrupt occurs, so the instruction after the CLI is from the interrupt handler. ...
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1answer
323 views

pipeline execution time

Lets suppose that 20 percent of the instructions in a program are branch instructions.The static prediction of the jumps supposes that the jumps don't happen. I should find the execution time in two ...
1
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1answer
158 views

Pipelining and Preemption

According to the concepts of Pipelining, In a single cycle different stages of different instructions are executed. Now I have a bit of confusion here, that if a single processing element is ...
2
votes
1answer
1k views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
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1answer
2k views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...