Questions tagged [cpu-pipelines]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
0
votes
0answers
14 views

Superscalar design on SimpleScalar simulation

I've learnt theoretically Computer Architecture at uni.However I can't wrap my head around it in practice. I am using Simple Scalar tool to simulate a benchmark program with configurable computer ...
0
votes
1answer
15 views

MIPS pipeline: MEM stage takes one cycle?

Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle: 1 cycle to read a register 4 cycles to reach to L1 cache 10 ...
0
votes
0answers
54 views

Why we need CPU registers with pipeline?

I understand how CPUs work in general in RiscV, but things got a little complicated with pipeline and I don't get it why we need registers at all. For example, let's look at: When the ALU's input was ...
1
vote
1answer
62 views

How can an instruction be fetched every cycle?

From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
0
votes
1answer
30 views

Why does this branch data hazard happen during the instruction decode stage?

Suppose I have the following MIPS code on a CPU with forwarding enabled: ...
1
vote
0answers
28 views

Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
0
votes
1answer
113 views

Does higher cpi give better performance?

Does higher cpi give better performance? Lets say there is a code and we can run it by 3 methods. 1 cpi for single cycle 99 cpi for multi cycle 70 cpi for pipeline Multi cycle has the highest cpi for ...
0
votes
1answer
31 views

Is pipeline bubbling only used with RAW data hazards?

I am studying computer science at university and we have an exam, which consists of several problems, one of which has to deal with pipelines. My understanding is that one effective way to solve data ...
0
votes
1answer
106 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
0
votes
0answers
20 views

MIPS pipelining stage used for commands

lw $4, 40($4) sw $4, 50($4) add $4, $4, $4 Suppose the above code was to be executed using 5 stage pipelining. I want to determine the data hazards but I am ...
0
votes
0answers
34 views

Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
0
votes
1answer
30 views

Dividing EX stage of a pipeline into EX1 and EX2 stages

There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be: In the five stage pipeline with forwarding support to EX, the first operand of ALU ...
1
vote
1answer
24 views

Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
1
vote
1answer
31 views

Why does taking advantage of locality matter in multithreaded systems?

As we all know, when a given thread/process reaches a memory address it does not have cached, the execution will (for the most part) freeze up until said data is fetched from memory. What I don't ...
0
votes
1answer
66 views

When the stall is actually going to happen?

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
0
votes
0answers
23 views

How to help compiler do pipelining?

I don't mean compiler flags for pipelining. I would like to program in a way that helps the compiler do optimizations using pipelining. I mean I want to order instructions in C in such a way that GCC (...
0
votes
1answer
22 views

About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor. We do assume that ...
1
vote
0answers
147 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
-1
votes
1answer
424 views

Calculating the pipeline speed up in case we have an infinite amount of stages

I have the following question: We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of ...
0
votes
1answer
52 views

Why cannot Operand forwarding remove all RAW hazards?

I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
0
votes
2answers
2k views

How to improve the CPI and Speed up factor in CPU-OS simulator?

I am using the CPU-OS simulator by Besim Mustafa(https://www.merlot.org/merlot/viewMaterial.htm?id=476196) and I am studying Pipeline Stages. I have written a simple program and captured the metrics ...
1
vote
0answers
42 views

How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
2
votes
0answers
23 views

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
0
votes
1answer
52 views

MIPS pipeline: choosing between slowing down a stage and adding a new stage

Suppose a new, more complicated, instruction is desired for this simple pipelined MIPS processor. Suppose, also, it could be implemented by either (a) adding new logic to the execute stage of the ...
-1
votes
1answer
15 views

Neural branch predictors linear, classical predictors exponential, in resources?

Wikipedia states: The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource ...
2
votes
1answer
124 views

How many RAW dependencies are present in these instructions?

What is the number of RAW dependencies in below set of instructions? I1: R1 = R2 - R3 I2: R2 = R1 + R3 I3: R3 = R1 + R2 I4: R1 = R2 - R2 I can see the following ...
0
votes
0answers
432 views

Deep pipeline - cpu architecture

I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance. While reading about vector instruction, I encountered the term deep ...
0
votes
2answers
268 views

How to make single cycle processor pipelined?

I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design. I suppose, that I should answer that what should be changed on ...
3
votes
2answers
428 views

How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
-1
votes
2answers
2k views

Confusion in speed up calculation for pipeline architecture

This is an online question I am trying to solve. You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
0
votes
1answer
101 views

Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
1
vote
1answer
2k views

In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
2
votes
2answers
103 views

Why reverse pipeline stages in cycle-level simulator?

In pipeline simulator exercise, it says that: Traversing the stages in backwards order simplifies the instruction flow through the pipeline. Also, in gpgpu-sim source code, the stages are reversed ...
0
votes
1answer
32 views

Case where anti-dependency doesn't need pipeline stalling

While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling. But i couldnt find at example for ...
1
vote
1answer
39 views

From where does the Fetch Unit get its instructions?

In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
1
vote
1answer
121 views

Data Hazard in Pipelining

To be precise I am here for RAW hazard. Consider a 5 stage pipeline . In case of $I_4-I_1$ dependency , I am not sure if it is an $RAW$ hazard as $I_4$ does not depends on value of $R_1$ that $...
0
votes
1answer
141 views

Any CPUs using value prediction, dynamic instruction reuse?

There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
0
votes
2answers
121 views

Branch Prediction question

My question relates to a video I watched on YouTube. The pipeline is a 5-stage pipeline which include fetch, decode, ALU, Mem (data), and Write. It mentions that nothing is fetched until we're sure ...
1
vote
1answer
576 views

Short pipeline or long pipeline

What is meant by a short pipeline? Does that mean the instructions are split into small number of pieces OR length of a piece is short?
2
votes
1answer
2k views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
2
votes
2answers
479 views

Difference between delayed branches and out-of-order execution

I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
2
votes
1answer
566 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
0
votes
1answer
279 views

Pipeline question

I have this multiple choice question from a computer architecture class, a mips processor executes a program at 10 sec, without pipelining and clock rate 100 MHz. When running the program on a ...
0
votes
1answer
29 views

What are the prerequisites for instruction pipelining to work?

When can it be applied? When can it not be used? I get the general idea but not what it takes to make it work.
0
votes
1answer
254 views

How is the control unit affected by pipelining? [closed]

Compared to not using instruction pipelining. What is different?
1
vote
0answers
632 views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
3
votes
1answer
124 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
0
votes
1answer
2k views

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
2
votes
1answer
436 views

The total time require for a pipeline to execute

The book says that a total time required for a pipeline with k stages to execute n instructions is as follows. $T _{k,n} =[pqnk+(1-pq)(k+n-1)] \tau$ p is the probability of encountering a branch ...
0
votes
2answers
193 views

predication execution, branch prediction

Below is a paragraph from a book. In an ordinary superscalar processor, we would use branch prediction to guess which of the given instructions is to be executed, and go down that path. If the ...